SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME

• US 20200135735A1
• Filed: 03/11/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Sengupta, Rwik, Hong, Joon Goo, Gerousis, Vassilios, Rodder, Mark S.
• Granted Patent: US 10,811,415 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.

Claims

1. A semiconductor device comprising:

a substrate;

a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and

a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.

2. The semiconductor device of claim 1, further comprising:

a third semiconductor layer over the substrate, the third semiconductor layer being a second type of semiconductor device different from the first type of semiconductor device; and

a fourth semiconductor layer over the substrate, the fourth semiconductor layer being the second type of semiconductor device.

3. The semiconductor device of claim 2, wherein a first portion of the third semiconductor layer overlaps the fourth semiconductor layer when viewed in the direction perpendicular to the plane of the substrate and a second portion of the third semiconductor layer is laterally offset from the fourth semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.

4. The semiconductor device of claim 2, wherein the first, second, third, and fourth semiconductor layers correspond to first, second, third, and fourth transistors, respectively.

5. The semiconductor device of claim 4, wherein a first portion of a gate region of the first and third transistors overlaps a gate region of the second and fourth transistors when viewed in the direction perpendicular to the plane of the substrate, and a second portion of the gate region of the first and third transistors is laterally offset from the gate region of the second and fourth transistors when viewed in the direction perpendicular to the plane of the substrate.

6. The semiconductor device of claim 1, wherein a first source or drain electrode corresponding to the first semiconductor layer contacts a first source or drain electrode corresponding to the second semiconductor layer, and a second source or drain electrode corresponding to the first semiconductor layer is laterally isolated from a second source or drain electrode corresponding to the second semiconductor layer.

7. The semiconductor device of claim 1, further comprising a buried power rail between the substrate and the first semiconductor layer.

8. A semiconductor device comprising:

a first semiconductor layer, the first semiconductor layer being a first type of semiconductor device;

a first gate region at least partially encapsulating the first semiconductor layer;

a second semiconductor layer over the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device; and

a second gate region at least partially encapsulating the second semiconductor layer, wherein the first semiconductor layer, a first portion of the first gate region, the second semiconductor layer, and the second gate region overlap when viewed along a z-direction, and a second portion of the first gate region is laterally offset from the second gate region when viewed along the z-direction.

9. The semiconductor device of claim 8, further comprising a substrate, wherein the first semiconductor layer, the first gate region, the second semiconductor layer, and the second gate region are formed over the substrate when viewed along the z-direction.

10. The semiconductor device of claim 9, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.

11. The semiconductor device of claim 9, further comprising:

a third semiconductor layer over the substrate, the third semiconductor layer being a second type of semiconductor device different from the first type of semiconductor device; and

a fourth semiconductor layer over the substrate, the fourth semiconductor layer being the second type of semiconductor device.

12. The semiconductor device of claim 11, wherein a first portion of the third semiconductor layer overlaps the fourth semiconductor layer when viewed in the direction perpendicular to a plane of the substrate and a second portion of the third semiconductor layer is laterally offset from the fourth semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.

13. The semiconductor device of claim 11, wherein the first, second, third, and fourth semiconductor layers correspond to first, second, third, and fourth transistors, respectively.

14. A method of making a semiconductor device, the method comprising:

forming a first semiconductor layer over a substrate, the first semiconductor layer being a first type of semiconductor device; and

forming a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.

15. The method of claim 14, further comprising:

forming a third semiconductor layer over the substrate, the third semiconductor layer being a second type of semiconductor device different from the first type of semiconductor device; and

forming a fourth semiconductor layer over the substrate, the fourth semiconductor layer being the second type of semiconductor device.

16. The method of claim 15, wherein a first portion of the third semiconductor layer overlaps the fourth semiconductor layer when viewed in the direction perpendicular to the plane of the substrate and a second portion of the third semiconductor layer is laterally offset from the fourth semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.

17. The method of claim 15, wherein the first, second, third, and fourth semiconductor layers correspond to first, second, third, and fourth transistors, respectively.

18. The method of claim 17, wherein a first portion of a gate region of the first and third transistors overlaps a gate region of the second and fourth transistors when viewed in the direction perpendicular to the plane of the substrate, and a second portion of the gate region of the first and third transistors is laterally offset from the gate region of the second and fourth transistors when viewed in the direction perpendicular to the plane of the substrate.

19. The method of claim 14, wherein a first source or drain electrode corresponding to the first semiconductor layer contacts a first source or drain electrode corresponding to the second semiconductor layer, and a second source or drain electrode corresponding to the first semiconductor layer is laterally isolated from a second source or drain electrode corresponding to the second semiconductor layer.

20. The method of claim 14, wherein at least one of the first or second semiconductor layer comprises a nanosheet layer, a nanowire layer, or a fin layer.