SEMICONDUCTOR STRUCTURE

• US 20200135737A1
• Filed: 01/24/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LIAW, Jhon-Jhy
• Granted Patent: US 11,004,852 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

Semiconductor structures are provided. A semiconductor structure includes a first P-type transistor including a first SiGe channel region, and a second P-type transistor including a second SiGe channel region. The first SiGe channel region has higher Ge atomic concentration than the second SiGe channel region. The first and second P-type transistors are formed in the same N-type well region.

Claims

1. A semiconductor structure, comprising:

a first P-type transistor comprising a first SiGe channel region; and

a second P-type transistor comprising a second SiGe channel region;

wherein the first SiGe channel region has higher Ge atomic concentration than the second SiGe channel region,

wherein the first and second P-type transistors are formed in the same N-type well region.

2. The semiconductor structure as claimed in claim 1, wherein the Ge atomic concentration of the first SiGe channel region is within a range of 15% to 35%, and the Ge atomic concentration of the second SiGe channel region is within a range of 5% to 14.5%.

3. The semiconductor structure as claimed in claim 1, wherein the Ge atomic concentration of the first SiGe channel region is within a range of 10.5% to 35%, and the Ge atomic concentration of the second SiGe channel region is within a range of 3% to 10%.

4. The semiconductor structure as claimed in claim 1, wherein the second P-type transistor is implemented in a SRAM cell of a chip.

5. The semiconductor structure as claimed in claim 1, wherein the second P-type transistor is implemented in I/O cell of a chip.

6. The semiconductor structure as claimed in claim 1, wherein source/drain regions of the first and second P-type transistors are formed by SiGe with Boron dopant, and the Ge atomic concentration of the source/drain regions of the first and second P-type transistors is higher than the Ge atomic concentrations of the first and second SiGe channel regions.

7. The semiconductor structure as claimed in claim 1, further comprising:

a plurality of N-type transistors,

wherein source/drain regions of the N-type transistors comprises at least one material selected from a group consisting of SiP, SiC, SiPC, SiAs, Si, and combinations thereof.

8. A semiconductor structure, comprising:

a first P-type transistor comprising a first SiGe channel region;

a second P-type transistor comprising a second SiGe channel region; and

a third P-type transistor comprising a Si-base channel region free of Ge,

wherein the first SiGe channel region has higher Ge atomic concentration than the second SiGe channel region,

wherein the first, second and third P-type transistors are formed in the same N-type well region.

9. The semiconductor structure as claimed in claim 8, wherein the third P-type transistor is implemented in a SRAM cell of a chip.

10. The semiconductor structure as claimed in claim 8, wherein the third P-type transistor is implemented in an I/O cell of a chip.

11. The semiconductor structure as claimed in claim 8, further comprising:

a plurality of N-type transistors,

wherein source/drain regions of the N-type transistors comprises at least one material selected from a group consisting of SiP, SiC, SiPC, SiAs, Si, and combinations thereof.

12. A semiconductor structure, comprising:

a first P-type transistor comprising a first SiGe channel region;

a second P-type transistor comprising a second SiGe channel region;

a third P-type transistor comprising a third SiGe channel region; and

a fourth P-type transistor comprising a fourth SiGe channel region,

wherein Ge atomic concentration of the first and third SiGe channel regions are identical, and higher than Ge atomic concentration of the second and fourth SiGe channel regions,

wherein the first and second channel regions are covered by a first work-function layer, and the third and fourth channel regions are covered by a second work-function layer different from the first work-function layer.

13. The semiconductor structure as claimed in claim 12, wherein the Ge atomic concentration of the first and third SiGe channel regions is within a range of 15% to 35%, and the Ge atomic concentration of the second and fourth SiGe channel regions is within a range of 5% to 14.5%.

14. The semiconductor structure as claimed in claim 12, wherein the second and fourth P-type transistors are implemented in SRAM cells of a chip.

15. The semiconductor structure as claimed in claim 12, wherein the second and fourth P-type transistors are implemented in I/O cells of a chip.

16. The semiconductor structure as claimed in claim 12, wherein source/drain regions of the first, second, third and fourth P-type transistors are formed by SiGe with Boron dopant, and the Ge atomic concentration of the source/drain regions of the first, second, third and fourth P-type transistors is higher than the Ge atomic concentrations of the first and second SiGe channel regions.

17. The semiconductor structure as claimed in claim 16, wherein the Ge atomic concentration of the source/drain regions of the first, second, third and fourth P-type transistors is within a range of 36% to 85%.

18. The semiconductor structure as claimed in claim 12, further comprising:

a plurality of N-type transistors,

wherein source/drain regions of the N-type transistors comprises at least one material selected from a group consisting of SiP, SiC, SiPC, SiAs, Si, and combinations thereof.

19. The semiconductor structure as claimed in claim 12, wherein the first, second, third and fourth P-type transistors are formed in the same N-type well region.

20. The semiconductor structure as claimed in claim 12, wherein the first P-type transistor is implemented in a first standard cell and the second P-type transistor is implemented in a second standard cell, and the first and second standard cells are electrically isolated by an isolation region.