High Density Vertical Thyristor Memory Cell Array with Improved Isolation
1. A method of manufacturing a memory cell array of vertical thyristor memory cells in a semiconductor substrate, the method comprising:
- etching a trench between vertical thyristor memory cells;
depositing insulating material non-conformally over the trench, the insulating material covering an electrically isolating core in the trench;
whereby the electrically isolating core and the insulating material in the trench isolates vertical thyristor memory cells on one side of the trench from vertical thyristor memory cells on the other side of the trench.
Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.
- 1. A method of manufacturing a memory cell array of vertical thyristor memory cells in a semiconductor substrate, the method comprising:
etching a trench between vertical thyristor memory cells; depositing insulating material non-conformally over the trench, the insulating material covering an electrically isolating core in the trench; whereby the electrically isolating core and the insulating material in the trench isolates vertical thyristor memory cells on one side of the trench from vertical thyristor memory cells on the other side of the trench.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
This patent application is a divisional of U.S. patent application Ser. No. 15/683,760, filed Aug. 22, 2017, issued as U.S. Pat. No. 10,535,657 on Jan. 14, 2020, which claims priority to U.S. Provisional Patent Application No. 62/378,098, entitled, “Vertical Thyristor Air Gap Isolation for High-Density Memories,” and filed Aug. 22, 2016. These applications are incorporated by reference along with all other references cited in this application.
This invention relates to semiconductor devices for information storage. In particular, it relates to vertical thyristors for use in static (SRAM) and dynamic random access memories (DRAM).
Semiconductor thyristor structures for SRAMs and DRAMs, and the processes for manufacturing them are described in several co-pending patent applications commonly assigned to the present assignee. See, e.g. U.S. patent application Ser. No. 14/590,852, entitled “Cross-Coupled Thyristor SRAM Semiconductor Structures and Methods of Fabrication,” issued as U.S. Pat. No. 9,613,968 on Apr. 4, 2017, which is incorporated herein by reference.
Various memory cell designs have been proposed based on the negative differential resistance behavior of a PNPN thyristor. An active or passive gate is often used in these designs for trade-offs among switching speed, retention leakage, or operation voltage. As the size of thyristor memory array cells becomes smaller, the isolation regions between adjoining memory cells also become smaller, reducing the extent of the electrical isolation provided by those regions. In closely spaced thyristors there is the possibility of adjoining cells interfering with each other through capacitive coupling, particularly if they are biased in opposite states. This interference can degrade the performance of the memory array, and in extreme cases even change the state of one of the thyristors.
This invention provides improved isolation between vertical thyristors to reduce cell interference by providing an air gap or a metal conductive shield between the thyristors, thus increasing memory array stability.
The present invention provides for an integrated circuit having an array of vertical thyristor memory cells in a semiconductor substrate with each vertical thyristor memory cell separated from other vertical thyristor memory cells by isolation regions. Each isolation region comprises a trench; an electrically isolating core in the trench; and insulating material surrounding the electrically isolating core. The isolation region electrically isolates the vertical thyristor memory cell from interference by operations of neighboring memory cells. The electrically isolating core may comprise an air tube along the trench or a conducting rod along the trench.
The present invention also provides for an integrated circuit having a semiconductor substrate. The integrated circuit comprises: a first thyristor having a vertically stacked P-conductivity type anode, N-conductivity type base, P-conductivity type base, and N-conductivity cathode provided by the semiconductor substrate; a second thyristor having a vertically stacked P-conductivity type anode, N-conductivity type base, P-conductivity type base, and N-conductivity cathode provided by the semiconductor substrate; and an isolation region separating the first thyristor from the second thyristor. The isolation region includes a trench extending into the semiconductor substrate below a junction region between the P-conductivity type base and the N-conductivity cathode of each of the first and second thyristors; an electrically isolating core in the trench; and insulating material surrounding the electrically isolating core so that the isolation region electrically isolates the first and second thyristors from interference by operation of the other thyristor. The electrically isolating core may comprise an air tube along the trench or an electrically conducting rod along the trench.
The present invention further provides for a method of manufacturing a memory cell array of vertical thyristors memory cell array in a semiconductor substrate. The method comprises etching a trench between vertical thyristor memory cells and depositing insulating material non-conformally over the trench, the insulating material covering an electrically isolating core in the trench. The electrically isolating core and the insulating material in the trench isolates the vertical thyristor memory cells on one of the trench from the vertical thyristor memory cells on the other side of the trench. The electrically isolating core can comprise air or a conducting material.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
Next, as shown in
As next shown in
Next, as shown in
The process flow continues to complete the elements of the vertical thyristors of the memory cell array with
Also shown in
The trenches 39 and 40 (
To improve the isolation between the memory cells, rather filling the trenches 39 and 40 completely with an insulating material, an air gap is provided in each of the trenches, according to one embodiment of the present invention. An air gap can be formed using various known semiconductor manufacturing processes. In one embodiment the trenches are etched such that the silicon is undercut with the hard mask/pad oxide 60 defining the trenches overhanging both sides of the etched trenches, as shown in
As yet another embodiment, a sacrificial material fill and spacer method can be used to create the air gaps in a more controlled manner. Starting with the structure shown in
The result is that silicon dioxide 65 fills the deep trenches 39 with the air gap 70 trapped within the deep trenches. A similar set of operations are then performed after the shallow trenches 40 are etched. The shallow trenches 40 are filled by insulating silicon dioxide with a trapped air gap as previously described. At this point the process flow is equivalent or nearly equivalent to the process flow stage earlier described and represented by
Another embodiment of the present invention provides for a conducting plate substituted for the air gap with many of the same process steps earlier described. The conducting plate, a cross-section of a conducting rod, is electrically grounded by connection along a location along the trench in which the conducting rod sits. To manufacture the conducting plate, silicon dioxide is again grown conformally on the sides and bottom of the deep etched trenches 39 and a sidewall oxidation process is performed to cover the sides of the trenches 39. Following that step, a conducting material 72, such as doped polysilicon, metals including tungsten and cobalt, or alloys including molybdenum-tungsten, titanium-tungsten, is deposited and recessed in the trench. The conducting material 72 appearing as a field plate in cross-section is part of a conducting rod in the deep trenches 39. The conducting material can be deposited using one of the well-known methods in the art, such as CVD or Physical Vapor Deposition (PVD) in the case of metal and silicides. Post deposition, an anisotropic dry etch is used to recess the conducting material such that its top surface is 10 nm to 80 nm below the silicon surface. Finally a non-conformal chemical vapor deposition (CVD) step which deposits a layer of silicon dioxide across the top of the structure, enclosing the conducting rods in the trenches. After the deep trenches 39 with the embedded conductors are formed, the shallower trenches 40 can be etched and filled in a similar manner. A chemical-mechanical planarization (CMP) step then planarizes the silicon dioxide layer and the N− layers 54 and P+(anode) layers 52 are created in the vertical thyristors, as previously described. The result is illustrated in
Hence the present invention provides for the closer packing of vertical thyristor memory cells in an array. The memory cells remain isolated as the memory cells are moved closer together without electrical interference between the cells. Since air has the lowest dielectric constant of all known materials, thyristor memory cell arrays with trench air gaps can significantly reduce the cross-coupling of neighboring cells and therefore provide a better immunity against electrical disturbance. With the embedded conductor design, on the other hand, electric field lines are either terminated at the conductor or bent away from it and therefore neighboring cell interference is reduced. In addition, the conductor can be either be either electrically floating or biased at a given voltage for better modulation of the thyristor memory cell operations.
This description of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the teaching above. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications. This description will enable others skilled in the art to best utilize and practice the invention in various embodiments and with various modifications as are suited to a particular use. The scope of the invention is defined by the following claims.