High Density Vertical Thyristor Memory Cell Array with Improved Isolation

• US 20200135738A1
• Filed: 12/30/2019
• Published: 04/30/2020
• Est. Priority Date: 08/22/2016
• Status: Active Grant

• Current Assignee: Tc Lab, Inc.
• Original Assignee: Tc Lab, Inc.
• Inventors: Luan, Harry, Axelrad, Valery
• Granted Patent: US 11,282,840 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: H01L 27/0817 Thyristors only
• CPC Class Codes: H01L 27/1027 Thyristors
• CPC Class Codes: H01L 29/66371 structurally associated with another device, e.g. built-in diode making integrated circuits H01L21/82
• CPC Class Codes: H10B 10/10 SRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 53/50 characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

Claims

1. A method of manufacturing a memory cell array of vertical thyristor memory cells in a semiconductor substrate, the method comprising:

etching a trench between vertical thyristor memory cells;

depositing insulating material non-conformally over the trench, the insulating material covering an electrically isolating core in the trench;

whereby the electrically isolating core and the insulating material in the trench isolates vertical thyristor memory cells on one side of the trench from vertical thyristor memory cells on the other side of the trench.

2. The method of claim 1 wherein the electrically isolating core comprises air.

3. The method of claim 1 wherein the electrically isolating core comprises a conducting material.

4. The method of claim 1 wherein the step of depositing insulating material non-conformally over the trench comprises a chemical vapor deposition (CVD) step.

5. The method of claim 1 wherein the step of etching a trench comprises etching the trench with overhanging sides of the etched trench.

6. The method of claim 5 wherein the step of depositing insulating material non-conformally comprises a plasma-enhanced chemical vapor deposition (PECVD) of silicon dioxide.

7. The method of claim 6 wherein the plasma-enhanced chemical vapor deposition (PECVD) of silicon dioxide creates air gaps in the trench.

8. The method of claim 1 between the step of etching a trench and the step of depositing insulating material non-conformally, further comprising:

lining the etched trench with an oxide layer; and

depositing a sacrificial material in the lined etched trench.

9. The method of claim 8 wherein the sacrificial material comprises polysilicon or carbon.

10. The method of claim 8 further comprising:

etching the sacrificial material such that a top surface of the sacrificial material is below a mask defining the trench.

11. The method of claim 10 wherein the step of etching the sacrificial material comprises etching the sacrificial material such that the top surface of the sacrificial material is below the mask defining the trench in a range of 10 nm to 50 nm.

12. The method of claim 11 wherein the step of etching the sacrificial material comprises a dry etch process.

13. The method of claim 10 further comprising:

conformally depositing and anisotropically etching an oxide film to form spacers along the sides of openings in the trench.

14. The method of claim 13 further comprising:

removing the sacrificial material in the trench.

15. The method of claim 14 wherein the step of removing the sacrificial material comprises isotropically etching the sacrificial material to form the trench with overhanging sides.

16. The method of claim 15 wherein the step of depositing insulating material non-conformally over the trench comprises a chemical vapor deposition (CVD) step.

17. The method of claim 1 between the step of etching a trench and the step of depositing insulating material non-conformally, further comprising:

depositing a conducting material in the trench whereby the conducting material forms a conducting plate to electrically isolate isolates the vertical thyristor memory cells on one side of the trench from vertical thyristor memory cells on the other side of the trench.

18. The method of claim 17 wherein the conducting material comprises doped polysilicon, metal or an alloy.

19. The method of claim 17 wherein the step of depositing the conducting material comprises a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process.

20. The method of claim 17 further comprising:

etching the conducting material in the trench such that a top surface of the conducting material is recessed below a top surface of the thyristor memory cells in a predetermined range.

21. The method of claim 20 wherein the predetermined range comprises a range of 10 nm to 80 nm.

22. The method of claim 17 further comprising:

prior to the step of depositing the conducting material, growing silicon dioxide to line the sides and bottom of the trench.