SRAM Structure and Connection
First Claim
1. A semiconductor structure, comprising:
- a static random-access memory (SRAM) circuit formed on a semiconductor substrate, having SRAM bit cells, bit-line edge cells, and word-line edge cells, wherein the SRAM cells are arranged in an array of columns and rows, are bordered by the bit-line edge cells on column edges, and are bordered by the word-line edge cells on row edges, each of the SRAM bit cells including two inverters cross-coupled together and a pass gate coupled to the two inverters, and the pass gate including a field-effect transistor (FET);
a first bit-line of a first metal material, disposed in a first metal layer, and electrically connected to a drain feature of the FET;
a first word-line of a second metal material, and electrically connected to a gate electrode of the FET, and disposed in a second metal layer over the first metal layer; and
a second bit-line of a third metal material, electrically connected to the first bit-line, and disposed in a third metal layer over the second metal layer, wherein the first metal material and the third metal material are different from each other in composition.
1 Assignment
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Accused Products
Abstract
A semiconductor structure includes SRAM cells, bit-line edge cells, and word-line edge cells, wherein the SRAM cells are arranged in an array, bordered by the bit-line edge cells and the word-line edge cells, each of the SRAM cells including two inverters cross-coupled together and a pass gate coupled to the two inverters, and the pass gate includes a FET; a first bit-line of a first metal material, disposed in a first metal layer, and electrically connected to a drain feature of the FET; a first word-line of a second metal material, and electrically connected to a gate electrode of the FET, and disposed in a second metal layer; and a second bit-line of a third metal material, electrically connected to the first bit-line, and disposed in a third metal layer. The first metal material and the third metal material are different from each other in composition.
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Citations
20 Claims
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1. A semiconductor structure, comprising:
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a static random-access memory (SRAM) circuit formed on a semiconductor substrate, having SRAM bit cells, bit-line edge cells, and word-line edge cells, wherein the SRAM cells are arranged in an array of columns and rows, are bordered by the bit-line edge cells on column edges, and are bordered by the word-line edge cells on row edges, each of the SRAM bit cells including two inverters cross-coupled together and a pass gate coupled to the two inverters, and the pass gate including a field-effect transistor (FET); a first bit-line of a first metal material, disposed in a first metal layer, and electrically connected to a drain feature of the FET; a first word-line of a second metal material, and electrically connected to a gate electrode of the FET, and disposed in a second metal layer over the first metal layer; and a second bit-line of a third metal material, electrically connected to the first bit-line, and disposed in a third metal layer over the second metal layer, wherein the first metal material and the third metal material are different from each other in composition. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor structure, comprising:
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a static random-access memory (SRAM) circuit formed on a semiconductor substrate, having SRAM bit cells, bit-line edge cells, and word-line edge cells, wherein the SRAM bit cells are arranged in an array of columns and rows, are bordered by the bit-line edge cells on column edges, and are bordered by the word-line edge cells on row edges, each of the SRAM bit cells including two inverters cross-coupled together and a pass gate connected to the two inverters, and wherein the pass gate includes a field-effect transistor (FET); and an interconnection structure having multiple metal layers and disposed on the SRAM circuit;
wherein the interconnection structure includes a first metal layer, a second metal layer disposed on the first metal layer, a third metal layer disposed on the second metal layer and a fourth metal layer disposed on the third metal layer, whereinthe first metal layer includes a first bit-line of a first metal material, and electrically connected to a drain feature of the FET, the second metal layer includes a first word-line of a second metal material, and electrically connected to a gate electrode of the FET, the third metal layer includes a second bit-line of a third metal material, and electrically connected to the first bit-line, the fourth metal layer includes a second word-line of a fourth metal material, and electrically connected to the first word-line, and the first metal material has a resistivity greater than a resistivity of the third metal material. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A semiconductor structure, comprising:
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a static random-access memory (SRAM) circuit formed on a semiconductor substrate, having a SRAM array, a bit-line edge strap, and a word-line edge strap, wherein the SRAM array includes SRAM bit cells configured in an array spanning along a first direction and a second direction, wherein the bit-line strap includes bit-line edge cells lined along the second direction and disposed on a first edge of the SRAM array, wherein the word-line strap includes word-line edge cells lined along the first direction and disposed on a second edge of the SRAM array, wherein the SRAM bit cells include two inverters cross-coupled together and a pass gate connected to the two inverters, and wherein the pass gate includes a field-effect transistor (FET); a first bit-line of a first metal material, disposed in a first metal layer, and electrically connected to drain features of pass gates of the SRAM cells; a first word-line of a second metal material, and electrically connected to a gate electrode of the FET, and disposed in a second metal layer over the first metal layer; a second bit-line of a third metal material, disposed in a third metal layer over the second metal layer, wherein the first metal material and the third metal material are different from each other in composition; and a transistor that includes a source connected to the first bit-line, a drain connected to the second bit-line, and a gate electrode connected to a signal line to control a connection between the first and second bit-lines.
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Specification