SRAM Structure and Connection

• US 20200135741A1
• Filed: 05/16/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy
• Granted Patent: US 10,868,018 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53242 the principal metal being a noble metal, e.g. gold
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor structure includes SRAM cells, bit-line edge cells, and word-line edge cells, wherein the SRAM cells are arranged in an array, bordered by the bit-line edge cells and the word-line edge cells, each of the SRAM cells including two inverters cross-coupled together and a pass gate coupled to the two inverters, and the pass gate includes a FET; a first bit-line of a first metal material, disposed in a first metal layer, and electrically connected to a drain feature of the FET; a first word-line of a second metal material, and electrically connected to a gate electrode of the FET, and disposed in a second metal layer; and a second bit-line of a third metal material, electrically connected to the first bit-line, and disposed in a third metal layer. The first metal material and the third metal material are different from each other in composition.

Claims

1. A semiconductor structure, comprising:

a static random-access memory (SRAM) circuit formed on a semiconductor substrate, having SRAM bit cells, bit-line edge cells, and word-line edge cells, wherein the SRAM cells are arranged in an array of columns and rows, are bordered by the bit-line edge cells on column edges, and are bordered by the word-line edge cells on row edges, each of the SRAM bit cells including two inverters cross-coupled together and a pass gate coupled to the two inverters, and the pass gate including a field-effect transistor (FET);

a first bit-line of a first metal material, disposed in a first metal layer, and electrically connected to a drain feature of the FET;

a first word-line of a second metal material, and electrically connected to a gate electrode of the FET, and disposed in a second metal layer over the first metal layer; and

a second bit-line of a third metal material, electrically connected to the first bit-line, and disposed in a third metal layer over the second metal layer, wherein the first metal material and the third metal material are different from each other in composition.

2. The semiconductor structure of claim 1, wherein the first metal material has a resistivity greater than a resistivity of the third metal material.

3. The semiconductor structure of claim 2, wherein

the first metal material includes one of ruthenium, cobalt, and molybdenum;

and

the third metal material includes copper.

4. The semiconductor structure of claim 2, wherein the first bit-line is barrier-free, and the second bit-line further includes a barrier layer surrounding the third metal material.

5. The semiconductor structure of claim 4, wherein the barrier layer includes one of titanium and titanium nitride (Ti/TiN), tantalum and tantalum nitride (Ta/TaN), and Ru.

6. The semiconductor structure of claim 2, further comprising:

first via features disposed underlying the first metal layer, the drain of the FET being electrically connected to the first bit-line through one of the first via features;

second via features vertically connecting first metal lines of the first metal layer to second metal lines of the second metal layer; and

third via features vertically connecting the second metal lines of the second metal layer to third metal lines of the third metal layer, wherein

the first bit-line in the first metal layer is electrically connected to the second bit-line in the third metal layer through a first one of the second via features, a first one of the second metal lines, and a first one of the third via features, and

the first one of the second via features and the first one of the third via features are disposed within the bit-line edge cells.

7. The semiconductor structure of claim 6, further comprising a bit-line strap inserted in the SRAM array, wherein the first bit-line is additionally connected to the second bit-line through a second one of the second via features, a second one of the second metal lines, and a second one of the third via features, and

the second one of the second via features and the second one of the third via features are disposed within the bit-line strap.

8. The semiconductor structure of claim 7, further comprising

a fourth metal layer of a fourth metal material, being disposed over the third metal layer;

fourth via features vertically connecting the third metal lines of the third metal layer to fourth metal lines of the fourth metal layer; and

a second word-line in the fourth metal layer, and electrically connected to the first word-line through a third one of the third via features, a first one of the third metal lines, and a first one of the fourth via features, wherein the third one of the third via features and the first one of the fourth via features are disposed within the word-line edge cells.

9. The semiconductor structure of claim 1, further comprising a write-enable unit coupled between the first and second bit-line and being operable to turn on/off a connection between the first and second bit-lines.

10. The semiconductor structure of claim 9, wherein the write-enable unit includes a transistor having a source connected to the first bit-line, a drain connected to the second bit-line, and a gate electrode connected to a signal line to turn on the transistor, thereby enabling the connection.

11. A semiconductor structure, comprising:

a static random-access memory (SRAM) circuit formed on a semiconductor substrate, having SRAM bit cells, bit-line edge cells, and word-line edge cells, wherein the SRAM bit cells are arranged in an array of columns and rows, are bordered by the bit-line edge cells on column edges, and are bordered by the word-line edge cells on row edges, each of the SRAM bit cells including two inverters cross-coupled together and a pass gate connected to the two inverters, and wherein the pass gate includes a field-effect transistor (FET); and

an interconnection structure having multiple metal layers and disposed on the SRAM circuit;

wherein the interconnection structure includes a first metal layer, a second metal layer disposed on the first metal layer, a third metal layer disposed on the second metal layer and a fourth metal layer disposed on the third metal layer, wherein

the first metal layer includes a first bit-line of a first metal material, and electrically connected to a drain feature of the FET,

the second metal layer includes a first word-line of a second metal material, and electrically connected to a gate electrode of the FET,

the third metal layer includes a second bit-line of a third metal material, and electrically connected to the first bit-line,

the fourth metal layer includes a second word-line of a fourth metal material, and electrically connected to the first word-line, and

the first metal material has a resistivity greater than a resistivity of the third metal material.

12. The semiconductor structure of claim 11, wherein the second metal material has a same composition to the first metal material and wherein the fourth metal material has a same composition to the third metal material.

13. The semiconductor structure of claim 12, wherein

the first metal material includes one of ruthenium, cobalt, and molybdenum;

and

the third metal material includes copper.

14. The semiconductor structure of claim 13, wherein

the second bit-line further includes a barrier layer surrounding the third metal material, and

the first bit-line is barrier-free, and the first metal material directly contacts an interlayer dielectric material.

15. The semiconductor structure of claim 14, wherein the barrier layer includes one of titanium and titanium nitride (Ti/TiN), and tantalum and tantalum nitride (Ta/TaN).

16. The semiconductor structure of claim 11, further comprising:

first via features disposed underlying the first metal layer, the drain of the FET being electrically connected to the first bit-line through one of the first via features;

second via features vertically connecting first metal lines of the first metal layer to second metal lines of the second metal layer; and

third via features vertically connecting the second metal lines of the second metal layer to third metal lines of the third metal layer, wherein

the first bit-line in the first metal layer is electrically connected to the second bit-line in the third metal layer through a first one of the second via features, a first one of the second metal lines, and a first one of the third via features, and

the first one of the second via features and the first one of the third via features are disposed within the bit-line edge cells.

17. The semiconductor structure of claim 11, further comprising a write-enable unit coupled between the first and second bit-line and being operable to turn on a connection between the first and second bit-lines.

18. The semiconductor structure of claim 17, wherein the write-enable unit includes a transistor, wherein the transistor includes a source connected to the first bit-line, a drain connected to the second bit-line, and a gate electrode connected to a signal line to turn on the transistor, thereby enabling the connection between the first and second bit-lines.

19. The semiconductor structure of claim 11, wherein the second, third and fourth metal materials have a same composition that is different from that of the first metal material.

20. A semiconductor structure, comprising:

a static random-access memory (SRAM) circuit formed on a semiconductor substrate, having a SRAM array, a bit-line edge strap, and a word-line edge strap, wherein the SRAM array includes SRAM bit cells configured in an array spanning along a first direction and a second direction, wherein the bit-line strap includes bit-line edge cells lined along the second direction and disposed on a first edge of the SRAM array, wherein the word-line strap includes word-line edge cells lined along the first direction and disposed on a second edge of the SRAM array, wherein the SRAM bit cells include two inverters cross-coupled together and a pass gate connected to the two inverters, and wherein the pass gate includes a field-effect transistor (FET);

a first bit-line of a first metal material, disposed in a first metal layer, and electrically connected to drain features of pass gates of the SRAM cells;

a first word-line of a second metal material, and electrically connected to a gate electrode of the FET, and disposed in a second metal layer over the first metal layer;

a second bit-line of a third metal material, disposed in a third metal layer over the second metal layer, wherein the first metal material and the third metal material are different from each other in composition; and

a transistor that includes a source connected to the first bit-line, a drain connected to the second bit-line, and a gate electrode connected to a signal line to control a connection between the first and second bit-lines.