MANUFACTURING METHOD OF STATIC RANDOM ACCESS MEMORY CELL

• US 20200135743A1
• Filed: 12/19/2019
• Published: 04/30/2020
• Est. Priority Date: 11/17/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HSU, Jordan, LIN, Yu-Kuan, LU, Shau-Wei, YANG, Chang-Ta, WANG, Ping-Wei, LO, Kuo-Hung
• Granted Patent: US 11,641,729 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A method for manufacturing a SRAM cell includes forming a first p-well in a semiconductor substrate; forming a first semiconductor fin extending within the first p-well; forming a first mask layer over the first semiconductor fin; patterning the first mask layer to expose a first channel region of the first semiconductor fin, while leaving a second channel region of the first semiconductor fin covered by the first mask layer; with the patterned first mask layer in place, doping the first channel region of the first semiconductor fin with a first dopant; after doping the first channel region of the first semiconductor fin, removing the first mask layer from the second channel region; and forming a first gate structure extending across the first channel region of the first semiconductor fin and a second gate structure extending across the second channel region of the first semiconductor fin.

Claims

1. A method for manufacturing a static random access memory (SRAM) cell comprising:

forming a first p-well in a semiconductor substrate;

forming a first semiconductor fin extending within the first p-well;

forming a first mask layer over the first semiconductor fin;

patterning the first mask layer to expose a first channel region of the first semiconductor fin, while leaving a second channel region of the first semiconductor fin covered by the first mask layer;

with the patterned first mask layer in place, doping the first channel region of the first semiconductor fin with a first dopant;

after doping the first channel region of the first semiconductor fin, removing the first mask layer from the second channel region; and

forming a first gate structure extending across the first channel region of the first semiconductor fin and a second gate structure extending across the second channel region of the first semiconductor fin.

2. The method of claim 1, further comprising prior to doping the first channel region of the first semiconductor fin, forming a shallow trench isolation (STI) structure that laterally surrounds a lower portion of the first semiconductor fin.

3. The method of claim 1, wherein the patterned first mask layer covers an entirety of a second p-well spaced part from the first p-well.

4. The method of claim 1, wherein the patterned first mask layer covers an entirety of an n-well bordering the first p-well.

5. The method of claim 1, further comprising doping the first and second channel regions of the first semiconductor fin with a second dopant prior to forming the first mask layer over the first semiconductor fin.

6. The method of claim 5, further comprising:

prior to doping the first and second channel regions of the first semiconductor fin with the second dopant, forming a shallow trench isolation (STI) that laterally surrounds a lower portion of the first semiconductor fin.

7. The method of claim 5, wherein the first and second dopants are the same dopant.

8. The method of claim 1, further comprising:

forming a second semiconductor fin extending within the first p-well;

forming a patterned second mask layer over the second semiconductor fin, while leaving the first semiconductor fin exposed; and

with the patterned second mask layer in place, doping the first semiconductor fin with a second dopant prior to forming the first mask layer.

9. The method of claim 8, wherein the second gate structure further extends across the second semiconductor fin.

10. The method of claim 8, wherein the second semiconductor fin remains covered by the first mask layer during doping the first channel region of the first semiconductor fin.

11. A method for manufacturing a static random access memory (SRAM) cell comprising:

forming a first p-well and a second p-well spaced from the first p-well by an n-well in a semiconductor substrate;

forming a first semiconductor fin extending within the first p-well and a second semiconductor fin extending within the second p-well;

doping the first and second semiconductor fins with a first dopant;

after doping the first and second semiconductor fins, forming a mask layer over the first and second semiconductor fins;

patterning the mask layer to expose the first semiconductor fin, while leaving the second semiconductor fin covered by the mask layer;

with the patterned mask layer in place, doping the first semiconductor fin with a second dopant;

after doping the first semiconductor fin, removing the mask layer from the second semiconductor fin; and

forming a first gate structure extending across the first semiconductor fin and a second gate structure extending across the second semiconductor fin.

12. The method of claim 11, wherein the patterned mask layer covers a channel region in the first semiconductor fin, the covered channel region is of a pass-gate transistor of a static random access memory (SRAM) cell.

13. The method of claim 11, wherein the patterned mask layer exposes a channel region in the first semiconductor fin, and the exposed channel region is of a pull-down transistor of a static random access memory (SRAM) cell.

14. The method of claim 11, wherein the patterned mask layer covers a first channel region and a second channel region in the second semiconductor fin, the first channel region is of a pull-down transistor of a static random access memory (SRAM) cell, and the second channel region is of a pass-gate transistor of the SRAM cell.

15. The method of claim 11, wherein the first and second dopants are the same dopant.

16. The method of claim 11, wherein the second dopant comprises boron or arsenic.

17. A method for manufacturing a static random access memory (SRAM) cell comprising:

forming a p-well within a write portion and a read portion within a semiconductor substrate;

forming a first semiconductor fin extending within the p-well within the write portion, and a second semiconductor fin extending within the p-well within the read portion;

forming a first mask layer covering the second semiconductor fin, while leaving the first semiconductor fin exposed;

with the first mask layer in place, doping the first semiconductor fin with a first dopant;

after doping the first semiconductor fin, removing the first mask layer from the second semiconductor fin;

after removing the first mask layer, forming a second mask layer covering the first semiconductor fin, while leaving the second semiconductor fin exposed; and

with the second mask layer in place, doping the second semiconductor fin with a second dopant.

18. The method of claim 17, wherein the second semiconductor fin has a lower doping concentration than the first semiconductor fin.

19. The method of claim 17, further comprising:

after doping the second semiconductor fin, removing the second mask layer from the first semiconductor fin; and

forming a gate structure extending across the first and second semiconductor fins.

20. The method of claim 19, wherein the gate structure forms a write-port pull-down transistor with the first semiconductor fin and a read-port pull-down transistor with the second semiconductor fin.