SRAM Cell with Balanced Write Port

• US 20200135744A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 06/16/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Kuo-Hsiu, Lin, Yu-Kuan, Chang, Feng-Ming, Hung, Lien Jung, Wang, Ping-Wei
• Granted Patent: US 11,678,474 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor device includes first, second, third, fourth, and fifth active regions each extending lengthwise along a first direction, wherein the first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors; and first, second, third, fourth, fifth, and sixth gates each extending lengthwise along a second direction perpendicular to the first direction, wherein the first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively, wherein the first, second, and fifth gates are electrically connected, and wherein one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, the third gate, and the fourth gate are electrically connected.

Claims

1. A semiconductor device, comprising:

first, second, third, fourth, and fifth active regions each extending lengthwise along a first direction, wherein the first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors; and

first, second, third, fourth, fifth, and sixth gates each extending lengthwise along a second direction perpendicular to the first direction, wherein the first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively, wherein the first, second, and fifth gates are electrically connected, and wherein one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, the third gate, and the fourth gate are electrically connected.

2. The semiconductor device of claim 1, wherein one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the fifth gate are electrically connected.

3. The semiconductor device of claim 1, wherein the first, second, third, fourth, and firth active regions are arranged in order from first to fifth along the second direction.

4. The semiconductor device of claim 3, wherein the first, second, and sixth gates are aligned on a straight line with the second gate between the first and sixth gates, and wherein the third, fourth, and fifth gates are aligned on another straight line with the fourth gate between the third and fifth gates.

5. The semiconductor device of claim 1, wherein the fifth active region is disposed between the second and third active regions.

6. The semiconductor device of claim 5, wherein the first, second, and fifth gates are aligned on a straight line with the second gate between the first and fifth gates, and wherein the third, fourth, and sixth gates are aligned on another straight line with the third gate between the fourth and sixth gates.

7. The semiconductor device of claim 1, wherein each of the first through fifth active regions comprises a fin, and each of the first through sixth transistors is a FinFET.

8. The semiconductor device of claim 1, wherein the first and second gates share a common metal layer, and wherein the third and fourth gates share another common metal layer.

9. A semiconductor device, comprising:

first, second, third, fourth, and fifth active regions arranged in order from first to fifth along a first direction, wherein the first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors; and

first, second, third, fourth, fifth, and sixth gates oriented along the first direction, wherein the first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively, wherein the first and second gates are connected, wherein the third, fourth, and fifth gates are aligned on a straight line with the fourth gate between the third and fifth gates, wherein the fourth gate is connected with the third gate but disconnected from the firth gate.

10. The semiconductor device of claim 9, wherein the first active region further comprises a channel region and S/D regions of a seventh transistor, and the fourth active region further comprises a channel region and S/D regions of an eighth transistor.

11. The semiconductor device of claim 10, further comprising seventh and eighth gates, wherein the seventh and eighth gates are configured to engage the channel regions of the seventh and eighth transistors respectively.

12. The semiconductor device of claim 11, wherein the seventh gate is aligned on the straight line with the third, fourth, and fifth gates, and the eighth gate is aligned on another straight line with the first, second, and sixth gates.

13. The semiconductor device of claim 9, wherein the first and fourth transistors are of a first conductivity type, the second and third transistors are of a second conductivity type opposite to the first conductivity type.

14. The semiconductor device of claim 13, wherein the fifth and sixth transistors are of a same conductivity type.

15. The semiconductor device of claim 9, further comprising:

one or more conductive features that electrically connect the second gate, one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the fifth gate.

16. The semiconductor device of claim 9, further comprising:

one or more conductive features that electrically connect the second gate, one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the sixth gate.

17. The semiconductor device of claim 9, further comprising:

one or more conductive features that electrically connect one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, and the third gate.

18. A semiconductor device, comprising:

first, second, third, and fourth FinFETs arranged in order from first to fourth along a first direction, wherein the first and fourth transistors are of a first conductivity type, the second and third transistors are of a second conductivity type opposite the first conductivity type, and each of the first through fourth transistors comprises a channel region, two source/drain (S/D) regions, and a gate stack over the respective channel region; and

fifth and sixth FinFETs between the second and third FinFETs, wherein the fifth and sixth FinFETs are of a same conductivity type, and each of the fifth and sixth transistors comprises a channel region, two source/drain (S/D) regions, and a gate stack over the respective channel region,

wherein the gate stacks of the first, second, and fifth FinFETs, one of the S/D regions of the third FinFET, and one of the S/D regions of the fourth FinFET are electrically connected.

19. The semiconductor device of claim 18, wherein the gate stacks of the third and fourth FinFETs, one of the S/D regions of the first FinFET, and one of the S/D regions of the second FinFET are electrically connected.

20. The semiconductor device of claim 18, wherein the first, second and fifth gate stacks share a common metal layer.