STACKED FINFET READ ONLY MEMORY

• US 20200135747A1
• Filed: 10/26/2018
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Reznicek, Alexander, Balakrishnan, Karthik
• Granted Patent: US 10,916,552 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/367 Gate dielectric programmed, e.g. different thickness
• CPC Class Codes: H10B 20/38 Doping programmed, e.g. mask ROM
• CPC Class Codes: H10B 20/50 having transistors on different levels, e.g. 3D ROM

Abstract

A stacked FinFET mask-programmable read only memory (ROM) is provided. The stacked FinFET mask-programmable ROM includes a fin structure extending upward from an insulator layer. The fin structure includes, from bottom to top, a first semiconductor fin portion, an insulator fin portion, and a second semiconductor fin portion. A lower gate structure having a first threshold voltage contacts a sidewall of the first semiconductor fin portion, and an upper gate structure having a second threshold voltage contacts a sidewall of the second semiconductor fin portion.

Claims

1. A stacked FinFET mask-programmable read only memory (ROM) comprising:

a fin structure extending upward from an insulator layer, wherein the fin structure comprises, from bottom to top, a first semiconductor fin portion, an insulator fin portion, and a second semiconductor fin portion;

a lower gate structure having a first threshold voltage and contacting a sidewall of the first semiconductor fin portion; and

an upper gate structure having a second threshold voltage and contacting a sidewall of the second semiconductor fin portion.

2. The stacked FinFET mask-programmable ROM of claim 1, wherein the first and second threshold voltages are the same.

3. The stacked FinFET mask-programmable ROM of claim 2, wherein the first semiconductor fin portion and the second semiconductor fin portion are both programmed as “

0”

.

4. The stacked FinFET mask-programmable ROM re of claim 2, wherein the first semiconductor fin portion and the second semiconductor fin portion are both programmed as “

1”

.

5. The stacked FinFET mask-programmable ROM of claim 2, wherein the lower gate structure and the upper gate structure comprise a same work function metal containing material.

6. The stacked FinFET mask-programmable ROM of claim 1, wherein the first and second threshold voltages are different.

7. The stacked FinFET mask-programmable ROM of claim 6, wherein the first semiconductor fin portion is programmed as “

0”

, and the second semiconductor fin portion is programmed as “

1”

.

8. The stacked FinFET mask-programmable ROM of claim 6, wherein the first semiconductor fin portion is programmed as “

1”

, and the second semiconductor fin portion is programmed as “

0”

.

9. The stacked FinFET mask-programmable ROM of claim 6, wherein the lower gate structure comprises a first work function metal containing material, and the upper gate structure comprises a second work function metal containing material that is compositionally different from the first work function metal containing material.

10. The stacked FinFET mask-programmable ROM of claim 1, wherein a portion of the lower gate structure contacts a lower portion of a sidewall of the insulator fin portion, and a portion of the upper gate structure contacts an upper portion of the sidewall of the insulator fin portion, and the lower and upper gate structures are in direct physical contact with each other.

12. The stacked FinFET mask-programmable ROM of claim 1, wherein the first semiconductor fin portion of the first fin structure is programmed as “

0”

, the second semiconductor fin portion of the first fin portion is programmed as “

0”

, the first semiconductor fin portion of the second fin structure is programmed as “

1”

, the second semiconductor fin portion of the second fin portion is programmed as “

0”

, the first semiconductor fin portion of the third fin structure is programmed as “

0”

, the second semiconductor fin portion of the third fin structure is programmed as “

1”

, the first semiconductor fin portion of the fourth fin structure is programmed as “

1”

, and the second semiconductor fin portion of the fourth fin structure is programmed as “

1”

.

11. A stacked FinFET mask-programmable read only memory (ROM) array comprising:

a first stacked FinFET mask-programmable ROM memory comprising a first fin structure extending upward from an insulator layer, wherein the first fin structure comprises, from bottom to top, a first semiconductor fin portion, an insulator fin portion, and a second semiconductor fin portion, a lower gate structure having a first threshold voltage contacts a sidewall of the first semiconductor fin portion of the first fin structure, and an upper gate structure having the first threshold voltage contacts a sidewall of the second semiconductor fin portion of the first fin structure;

a second stacked FinFET mask-programmable ROM memory comprising a second fin structure extending upward from the insulator layer, wherein the second fin structure comprises, from bottom to top, a first semiconductor fin portion, an insulator fin portion, and a second semiconductor fin portion, a lower gate structure having a second threshold voltage that is different from the first threshold voltage contacts a sidewall of the first semiconductor fin portion of the second fin structure, and an upper second gate structure having the first threshold voltage contacts a sidewall of the second semiconductor fin portion of the second fin structure;

a third stacked FinFET mask-programmable ROM memory comprising a third fin structure extending upward from the insulator layer, wherein the third fin structure comprises, from bottom to top, a first semiconductor fin portion, an insulator fin portion, and a second semiconductor fin portion, a lower gate structure having the first threshold voltage contacts a sidewall of the first semiconductor fin portion of the third fin structure, and an upper gate structure having the second threshold voltage contacts a sidewall of the second semiconductor fin portion of the third fin structure; and

a fourth stacked FinFET mask-programmable ROM memory comprising a fourth fin structure extending upward from the insulator layer, wherein the fourth fin structure comprises, from bottom to top, a first semiconductor fin portion, an insulator fin portion, and a second semiconductor fin portion, a lower gate structure having the second threshold voltage contacts a sidewall of the first semiconductor fin portion of the fourth fin structure, and an upper gate structure having the second threshold voltage and contacting a sidewall of the second semiconductor fin portion of the fourth fin structure.

13. A method of forming a stacked FinFET mask-programmable read only memory (ROM), the method comprising:

forming a fin structure extending upward from an insulator layer, wherein the fin structure comprises, from bottom to top, a first semiconductor fin portion, an insulator fin portion, and a second semiconductor fin portion;

forming a lower gate structure having a first threshold voltage and contacting a sidewall of the first semiconductor fin portion; and

forming an upper gate structure having a second threshold voltage and contacting a sidewall of the second semiconductor fin portion.

14. The method of claim 13, wherein the forming of the lower gate structure comprises:

forming an interlayer dielectric (ILD) material laterally surrounding and above the fin structure, wherein the ILD material has an opening the physically exposes the fin structure;

sequentially depositing a first gate dielectric material layer, a first work function setting layer and a first gate electrode layer in the opening; and

removing the first gate dielectric material layer, the first work function setting layer and the first gate electrode layer from the second semiconductor fin portion.

15. The method of claim 13, wherein the first and second threshold voltages are the same, and the lower gate structure and the upper gate structure comprise a same work function metal containing material.

16. The method of claim 15, wherein the first semiconductor fin portion and the second semiconductor fin portion are both programmed as “

0”

.

17. The method of claim 15 wherein the first semiconductor fin portion and the second semiconductor fin portion are both programmed as “

1”

.

18. The method of claim 13, wherein the first and second threshold voltages are different, and the lower gate structure comprises a first work function metal containing material, and the upper gate structure comprises a second work function metal containing material that is compositionally different from the first work function metal containing material.

19. The method of claim 18, wherein the first semiconductor fin portion is programmed as “

0”

, and the second semiconductor fin portion is programmed as “

1”

.

20. The method of claim 18, wherein the first semiconductor fin portion is programmed as “

1”

, and the second semiconductor fin portion is programmed as “

0”

.