MEMORY CELL PILLAR INCLUDING SOURCE JUNCTION PLUG

• US 20200135748A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 11/07/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Simsek-Ege, Fatma Arzum, Parat, Krishna K., Tran, Luan C., Kuo, Meng-Wei, Hu, Yushi
• Granted Patent: US 11,653,494 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/23 with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

Claims

1. An apparatus comprising:

a source material;

a dielectric material over the source material, the dielectric material including an opening;

a select gate material over the dielectric material;

a memory cell stack over the select gate material;

a conductive plug located in the opening of the dielectric material and contacting a portion of the source material; and

a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

2. The apparatus of claim 1, wherein the dielectric material includes a dielectric constant greater than a dielectric constant of silicon dioxide.

3. The apparatus of claim 1, further comprising an additional dielectric material surrounded by at least a portion of the channel material.

4. The apparatus of claim 1, wherein the source material includes a conductively-doped polysilicon.

5. The apparatus of claim 1, further comprising a silicon nitride material between the channel material and the select gate material.

6. The apparatus of claim 5, further comprising silicon dioxide material between the channel material and the select gate material.

7. The apparatus of claim 1, further comprising oxide-nitride-oxide (ONO) material between the channel material and the select gate material.

8. The apparatus of claim 1, wherein the select gate material includes conductively-doped polysilicon.

9. The apparatus of claim 1, further comprising an additional dielectric material located in a recess between the conductive plug and the dielectric material over the source material.

10. The apparatus of claim 9, further comprising polysilicon material in the recess.

11. The apparatus of claim 1, further comprising a transition metal combined with a semiconductor material, such that the source material is between the dielectric material and the transition metal combined with the semiconductor material.

12. The apparatus of claim 1, further comprising an additional select gate material over the memory cell stack.

13. An apparatus comprising:

a source material;

a first dielectric material over the source material, the first dielectric material including a dielectric constant greater than a dielectric constant of silicon dioxide;

a source-side select (SGS) gate material over the first dielectric material;

levels of memory cells over the SGS select gate material; and

a cell pillar extending through the levels of memory cells, the SGS gate material, and the first dielectric material, the cell pillar including a conductive plug contacting the source material, a channel material contacting the conductive plug, and a second dielectric material surrounded by at least a portion of the channel material.

14. The apparatus of claim 13, wherein the conductive plug has a thickness of at least one-half of a thickness of the first dielectric material.

15. The apparatus of claim 13, wherein the first dielectric material has a thickness greater than 30 nanometers.

16. The apparatus of claim 13, wherein the conductive plug includes conductively-doped semiconductor material of n-type.

17. The apparatus of claim 13, wherein the second dielectric material has a dielectric constant less than the dielectric constant of the first dielectric material.

18. The apparatus of claim 13, further comprising a substrate and a silicide material between the substrate and the source material.

19. A method comprising:

forming a source material;

forming a dielectric material over the source material;

forming a source-side select (SGS) gate material over the dielectric material;

forming alternating levels of materials over the SGS gate material;

forming a first portion of a cell pillar, the first portion of the cell pillar contacting the source material and located between the alternating levels of materials and the source material; and

forming a second portion of the cell pillar after the first portion of the cell pillar is formed, the second portion of the cell pillar contacting the first portion of the cell pillar and extending through the alternating levels of materials.

20. The method of claim 19, wherein the dielectric material has a dielectric constant greater than a dielectric constant of silicon dioxide.