THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF

• US 20200135753A1
• Filed: 12/14/2018
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Yangtze Memory Technologies Co., Ltd. (Yangtze River Storage Technology Holdings Co. , Ltd.)
• Original Assignee: Yangtze Memory Technologies Co., Ltd. (Yangtze River Storage Technology Holdings Co. , Ltd.)
• Inventors: ZHANG, Kun
• Granted Patent: US 11,024,641 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a temporary top selective gate cut in an upper portion of the alternating dielectric stack and extending along a lateral direction; forming a plurality of channel holes penetrating the alternating dielectric stack; removing the temporary top selective gate cut; and forming, simultaneously, a plurality of channel structures in the plurality of channel holes and a top selective gate cut structure.

Claims

1. A method for forming a three-dimensional (3D) memory device, comprising:

forming an alternating dielectric stack on a substrate;

forming a temporary top selective gate cut in an upper portion of the alternating dielectric stack and extending along a lateral direction;

forming a plurality of channel holes penetrating the alternating dielectric stack;

removing the temporary top selective gate cut; and

forming, simultaneously, a plurality of channel structures in the plurality of channel holes and a top selective gate cut structure.

2. The method of claim 1, wherein forming the alternating dielectric stack comprises:

forming at least 32 dielectric layer pairs stacked in a vertical direction, wherein each dielectric layer pair includes a first dielectric layer and a second dielectric layer that is different from the first dielectric layer.

3. The method of claim 1, wherein forming the temporary top selective gate cut comprises:

forming a trench in an upper portion of the alternating dielectric stack and extending along the lateral direction; and

forming a sacrificial wall in the trench.

4. The method of claim 3, wherein forming the trench comprises:

etching top three dielectric layer pairs of the alternating dielectric stack to form the trench.

5. The method of claim 3, wherein forming the sacrificial wall comprises:

disposing a filling material into the trench to form the sacrificial wall;

wherein the filling material is stable physically and chemically within a temperature range between about 200°

C. to about 400°

C.

6. The method of claim 5, wherein disposing the filling material comprises depositing a carbonaceous inorganic substance mixed with a solvent.

7. The method of claim 3, wherein removing the temporary top selective gate cut comprises:

performing an ashing process to simultaneously clean the plurality of channel holes and remove the sacrificial wall.

8. The method of claim 3, wherein simultaneously forming the plurality of channel structures and the top selective gate cut structure comprises:

simultaneously forming a functional layer on sidewalls of the plurality of channel holes and forming a dummy functional layer on sidewalls of the trench, followed by;

simultaneously forming a channel layer covering the functional layer in each channel hole and forming a dummy channel layer covering the dummy functional layer in the trench, followed by;

simultaneously forming a dielectric filling structure filling each channel hole and forming a dielectric filling wall filling the trench, followed by; and

simultaneously forming a channel plug on a top portion of each channel hole on the dielectric filling wall and forming a dummy channel strip cover on the dielectric filling wall in the trench.

9. The method of claim 8, further comprising:

before forming the functional layer, forming an epitaxial layer on a surface of the substrate that is exposed by the plurality of channel holes;

wherein;

the channel layer is in contact with the epitaxial layer in each channel hole;

each channel structure includes the epitaxial layer, the functional layer, the channel layer, the dielectric filling structure, and the channel plug; and

the top selective gate cut structure includes the dummy functional layer, the dummy channel layer, the dielectric filling wall, and the dummy channel strip cover.

10. The method of claim 8, wherein simultaneously forming the functional layer and the dummy functional layer comprises:

simultaneously forming a barrier layer on the sidewalls of the plurality of channel holes and forming a dummy barrier layer on the sidewalls of the trench, followed by;

simultaneously forming a storage layer on a surface of the barrier layer in each channel hole and forming a dummy storage layer on a surface of the dummy barrier layer in the trench, followed by; and

simultaneously forming a tunneling layer on a surface of the storage layer in each channel hole and forming a dummy tunneling layer on a surface of the dummy storage layer in the trench.

11. The method of claim 1, further comprising:

forming a pair of slits penetrating the alternating dielectric stack, the pair of slits being extended in parallel along the lateral direction;

wherein a number N of rows of channel structures are formed between the pair of slits, wherein each row of channel structures are arranged staggered with adjacent row of channel structures, and N is an even number; and

wherein the top selective gate cut structure is formed between number N/2 row of channel structures and number N/2+1 row of channel structures.

12. The method of claim 1, further comprising:

replacing the second dielectric layers in the alternating dielectric with conductive layers.

13. A three-dimensional (3D) memory device, comprising:

an alternating layer stack on a substrate;

a plurality of channel holes penetrating the alternating layer stack;

a channel structure in each channel hole; and

a top selective gate cut structure having a laminated structure and located between two rows of channel structures.

14. The device of claim 13, wherein the alternating layer stack comprises:

at least 32 conductive/dielectric layer pairs stacked in a vertical direction, wherein each conductive/dielectric pair includes a dielectric layer and a conductive layer.

15. The device of claim 13, wherein:

the top selective gate cut structure extends into three top conductive/dielectric layer pairs of the alternating layer stack.

16. The device of claim 13, wherein the channel structure comprises:

an epitaxial layer on a bottom of the channel hole;

a functional layer on a sidewall of the channel hole;

a channel layer covering a sidewall of the functional layer and being in contact with the epitaxial layer;

a dielectric filling structure covering a sidewall of the channel layer and filling the channel hole; and

a channel plug on a top portion of the channel hole.

17. The device of claim 16, wherein the top selective gate cut structure comprises:

a dummy functional layer covering sidewalls and a bottom of a trench;

a dummy channel layer covering the dummy functional layer;

a dielectric filling wall, and

a dummy channel strip cover on a top portion of the trench.

18. The device of claim 17, wherein:

the functional layer and the dummy functional layer have a same material and are formed in a same process;

the channel layer and the dummy channel layer have a same material and are formed in a same process;

a dielectric filling structure and the dielectric filling wall have a same material and are formed in a same process; and

the channel plug and the dummy channel strip cover have a same material and are formed in a same process.

19. The device of claim 16, wherein the functional layer comprises:

a barrier layer on the sidewall of the first channel hole configured to block an outflow of electronic charges;

a storage layer on a surface of the first barrier layer configured to store electronic charges during operation of the 3D memory device; and

a tunneling layer on a surface of the first storage layer configured to tunnel electronic charges.

20. The device of claim 13, further comprising:

a pair of slits penetrating the alternating layer stack, the pair of slits being extended in parallel along the lateral direction;

wherein a number N of rows of channel structures are located between the pair of slits, each row of channel structures are arranged staggered with adjacent row of channel structures, and N is an even number; and

wherein the top selective gate cut structure is located between number N/2 row of channel structures and number N/2+1 row of channel structures.