METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

• US 20200135754A1
• Filed: 05/09/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Jin Won
• Granted Patent: US 10,868,036 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Provided herein may be a method of manufacturing a semiconductor device including the step of replacing sacrificial layers of a stack with line patterns through slits that pass through the stack and have different depths.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a stack;

forming a first slit penetrating from a top surface of the stack into the stack to a first depth, and a second slit penetrating from the top surface of the stack into the stack to a second depth;

removing sacrificial layers of the stack through the first slit and the second slit that have different depths; and

filling areas from which the sacrificial layers have been removed with line patterns separated from each other by the first slit and the second slit.

2. The method according to claim 1,

wherein the stack comprises interlayer insulating layers and the sacrificial layers that are alternately stacked,

wherein the interlayer insulating layers and the sacrificial layers are divided into a first stack pattern and second stack patterns,

wherein the first stack pattern is disposed under the first slit and extends to overlap with the first slit, and

wherein the second stack patterns are disposed over the first stack pattern and separated from each other by the first slit.

3. The method according to claim 2, wherein the line patterns comprise:

word lines formed in areas from which first sacrificial layers included in the first stack pattern among the sacrificial layers have been removed; and

first select lines formed in areas from which second sacrificial layers included in the second stack patterns among the sacrificial layers have been removed.

4. The method according to claim 3, wherein the line patterns comprise:

second select lines formed in areas from which first sacrificial layers included in the first stack pattern among the sacrificial layers have been removed.

5. The method according to claim 2, further comprising forming channel structures passing through the stack,

wherein the channel structures shared by the first stack pattern are divided into channel groups surrounded by the respective second stack patterns.

6. The method according to claim 1, wherein each of the line patterns is formed of conductive material.

7. The method according to claim 1, wherein the second slit is formed to penetrate the stack to the second depth to pass through the stack.

8. The method according to claim 1, wherein the first depth is less than the second depth.

9. The method according to claim 1, wherein each of the line patterns includes tungsten.

10. A method of manufacturing a semiconductor device, comprising:

forming a first stack;

forming a second stack over the first stack;

forming slits passing through at least one of the first stack and the second stack such that a number of slits passing through the second stack is greater than a number of slits passing through the first stack;

removing first sacrificial layers of the first stack and second sacrificial layers of the second stack through the slits; and

filling areas from which the first sacrificial layers and the second sacrificial layers have been removed with line patterns through the slits.

11. The method according to claim 10,

wherein the first stack comprises first interlayer insulating layers and the first sacrificial layers that are alternately stacked,

wherein the second stack comprises second interlayer insulating layers and the second sacrificial layers that are alternately stacked.

12. The method according to claim 10, wherein the line patterns are formed of conductive material.

13. The method according to claim 10, further comprising forming channel structures passing through the first stack and the second stack,

wherein the slits are disposed adjacent to each other with one or more rows of the channel structures therebetween.

14. The method according to claim 10, wherein slits comprise:

first slits passing through the second stack; and

second slits disposed adjacent to each other with at least one of the first slits therebetween, and the second slits passing through the second stack and the first stack.

15. The method according to claim 10, wherein the line patterns include tungsten.