NONVOLATILE MEMORY DEVICE, VERTICAL NAND FLASH MEMORY DEVICE AND SSD DEVICE INCLUDING THE SAME

• US 20200135758A1
• Filed: 06/13/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Sang-Won, NAM, Sang-Wan, LIM, Bong-Soon
• Granted Patent: US 10,804,293 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.

Claims

1. A memory device, comprising:

a semiconductor substrate including a page buffer region;

a memory cell array formed in a memory cell region above the semiconductor substrate and including a plurality of memory cells;

a plurality of bitlines extending in a column direction above the memory cell array, each of the plurality of bitlines being cut into each of a plurality of first bitline segments and each of a plurality of second bitline segments;

a plurality of first vertical conduction paths extending in a vertical direction and penetrating a column-directional central region of the memory cell region, the plurality of first vertical conduction paths connecting the plurality of first bitline segments and the page buffer region; and

a plurality of second vertical conduction paths extending in the vertical direction and penetrating the column-directional central region, the plurality of second vertical conduction paths connecting the plurality of second bitline segments and the page buffer region.

2. The memory device as claimed in claim 1, wherein the memory cell array has a single mat structure that is a unit of a program operation, a read operation, and an erase operation.

3. The memory device as claimed in claim 1, wherein one of the plurality of first bitline segments and the plurality of second bitline segments is electrically connected to a plurality of page buffers included in the page buffer region during a program operation and a read operation.

4. The memory device as claimed in claim 1, wherein both of the plurality of first bitline segments and the plurality of second bitline segments are electrically connected to a plurality of page buffers included in the page buffer region during an erase operation.

5. The memory device as claimed in claim 1, wherein the memory cell array includes a plurality of cell strings, each cell string including memory cells arranged in a vertical direction, and the memory device is a vertical NAND flash memory device.

6. The memory device as claimed in claim 5, wherein the column-directional central region of the memory cell region corresponds to a gate cut region, and the plurality of first vertical conduction paths and the plurality of second vertical conduction paths are formed in the gate cut region.

7. The memory device as claimed in claim 1, wherein the page buffer region includes:

a plurality of page buffers;

a plurality of first switches configured to electrically connect the plurality of first vertical conduction paths and the plurality of page buffers in response to a first switch signal; and

a plurality of second switches configured to electrically connect the plurality of second vertical conduction paths and the plurality of page buffers in response to a second switch signal.

8. The memory device as claimed in claim 7, wherein one of the plurality of first switches and the plurality of second switches is selectively turned on in a program operation and a read operation.

9. The memory device as claimed in claim 7, wherein both of the plurality of first switches and the plurality of second switches are turned on in an erase operation.

10. The memory device as claimed in claim 7, further comprising:

a switch control circuit configured to generate the first switch signal and the second switch signal based on a mode signal indicating a program operation, a read operation, or an erase operation and an access address determining selected memory cells among the plurality of memory cells.

11. The memory device as claimed in claim 10, wherein the memory cell array is divided into a first sub array connected to the plurality of first bitline segments and a second sub array connected to the plurality of second bitline segments.

12. The memory device as claimed in claim 11, wherein, when the mode signal indicates the program operation or the read operation, the switch control circuit activates selectively one of the first switch signal and the second switch signal based on one address bit among bits of the access address, the one address bit indicating whether the selected memory cells are included in the first sub array or the second sub array.

13. The memory device as claimed in claim 11, wherein, when the mode signal indicates the program operation or the read operation, the switch control circuit activates selectively one of the first switch signal and the second switch signal based on string selection signals provided by decoding the access address.

14. The memory device as claimed in claim 11, wherein, when the mode signal indicates the erase operation, the switch control circuit activates both of the first switch signal and the second switch signal regardless of the access address.

15. The memory device as claimed in claim 10, wherein:

the memory cell array includes a plurality of cell strings, each cell string including memory cells arranged in a vertical direction, and

the switch control circuit includes;

a first logic gate configured to perform a logic operation on an inversion bit of an uppermost string selection bit and a mode signal to generate the first switch signal, the uppermost string selection bit being a most significant bit among string selection bits determining selected cell strings among the plurality of cell strings, the mode signal indicating a program operation, a read operation, or an erase operation; and

a second logic gate configured to perform a logic operation on the uppermost string selection bit and the mode signal to generate the second switch signal.

16. The memory device as claimed in claim 10, wherein:

the memory cell array is divided into a first sub array connected to the plurality of first bitline segments and a second sub array connected to the plurality of second bitline segments, and the memory cell array includes a plurality of cell strings, each cell string including memory cells arranged in a vertical direction, and

the switch control circuit includes;

a first logic gate configured to perform a logic operation on first string selection signals that select the cell strings in the first sub array;

a second logic gate configured to perform a logic operation on second string selection signals that select the cell strings in the second sub array;

a third logic gate configured to perform a logic operation on an output of the first logic gate and a mode signal indicating a program operation, a read operation, or an erase operation to generate the first switch signal; and

a fourth logic gate configured to perform a logic operation on an output of the second logic gate and the mode signal to generate the second switch signal.

17. The memory device as claimed in claim 1, wherein the page buffer region includes:

a plurality of page buffers that are arranged in a matrix of a plurality of rows and a plurality of columns;

a plurality of first switches configured to electrically connect the plurality of first vertical conduction paths and the plurality of page buffers in response to a first switch signal; and

a plurality of second switches configured to electrically connect the plurality of second vertical conduction paths and the plurality of page buffers in response to a second switch signal.

18. The memory device as claimed in claim 17, wherein the bitlines connected to the page buffers of the same column are cut sequentially along a diagonal direction making an acute angle with the column direction.

19. A vertical NAND flash memory device having a cell over periphery (COP) structure in which a peripheral circuit is formed on a semiconductor substrate and a memory cell array is stacked on the peripheral circuit, the vertical NAND flash memory device comprising:

a semiconductor substrate including a page buffer region;

a memory cell array formed in a memory cell region above the semiconductor substrate and including a plurality of cell strings, each cell string including memory cells arranged in a vertical direction;

a plurality of bitlines extending in a column direction above the memory cell array, each of the plurality of bitlines being cut into each of a plurality of first bitline segments and each of a plurality of second bitline segments;

a plurality of first vertical conduction paths extending in a vertical direction and penetrating a column-directional central region of the memory cell region, the plurality of first vertical conduction paths connecting the plurality of first bitline segments and the page buffer region; and

a plurality of second vertical conduction paths extending in the vertical direction and penetrating the column-directional central region, the plurality of second vertical conduction paths connecting the plurality of second bitline segments and the page buffer region.

20. A solid state drive (SSD), comprising:

a plurality of nonvolatile memory devices; and

an SSD controller configured to control the plurality of nonvolatile memory devices,

at least one of the plurality of nonvolatile memory devices including;

a semiconductor substrate including a page buffer region;

a memory cell array formed in a memory cell region above the semiconductor substrate and including a plurality of memory cells;

a plurality of bitlines extending in a column direction above the memory cell array, each of the plurality of bitlines being cut into each of a plurality of first bitline segments and each of a plurality of second bitline segments;

a plurality of first vertical conduction paths extending in a vertical direction and penetrating a column-directional central region of the memory cell region, the plurality of first vertical conduction paths connecting the plurality of first bitline segments and the page buffer region; and

a plurality of second vertical conduction paths extending in the vertical direction and penetrating the column-directional central region, the plurality of second vertical conduction paths connecting the plurality of second bitline segments and the page buffer region.