METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20200135759A1
• Filed: 06/14/2019
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHOI, Eun Yeoung, KIM, Hyung Joon, JEE, Jung Geun
• Granted Patent: US 11,094,709 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A hole is formed to pass through preliminary first mold layers and preliminary second mold layers to form first mold layers and mold layers respectively that are alternately stacked in a vertical direction, perpendicular to a lower structure, on the lower structure. The first mold layers are partially etched along a side surface of the hole to form recess regions and recessed first mold layers. Third mold layers are formed in the recess regions to form interlayer insulation layers so that each of the interlayer insulation layers includes a corresponding third mold layer and a corresponding recessed first mold layer that are positioned at the same level in the vertical direction. A first dielectric layer is formed in the hole to cover the third mold layers and the second mold layers stacked on each other. Information storage patterns are formed on the first dielectric layer.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming a hole passing through a plurality of preliminary first mold layers and a plurality of preliminary second mold layers to form a plurality of first mold layers and a plurality of second mold layers respectively that are alternately stacked in a vertical direction, perpendicular to a lower structure, on the lower structure;

partially etching the plurality of first mold layers along a side surface of the hole to form a plurality of recess regions and a plurality of recessed first mold layers;

forming a plurality of third mold layers in the plurality of recess regions to form a plurality of interlayer insulation layers so that each of the plurality of interlayer insulation layers includes a corresponding third mold layer of the plurality of third mold layers and a corresponding recessed first mold layer of the plurality of recessed first mold layers that are positioned at the same level in the vertical direction; and

forming a first dielectric layer in the hole, the first dielectric layer covering the plurality of third mold layers and the plurality of second mold layers stacked on each other; and

forming a plurality of information storage patterns on the first dielectric layer.

2. The method of claim 1,

wherein each of the plurality of third mold layers fills a corresponding recessed region of the plurality of recessed regions, the corresponding recessed region being disposed between two adjacent second mold layers of the plurality of second mold layers, and extends into the hole beyond side surfaces of the two adjacent second mold layers.

3. The method of claim 2,

wherein each of the plurality of third mold layers has a rounded corner in the hole.

4. The method of claim 1,

wherein the first dielectric layer is conformally formed on side surfaces of the plurality of third mold layers and side surfaces of the plurality of second mold layers;

and

the plurality of information storage patterns are spaced apart from each other in the vertical direction, and each of the plurality of information storage patterns is positioned at the same level in the vertical direction with a corresponding second mold layer of the plurality of second mold layers.

5. The method of claim 1,

wherein the forming of the plurality of third mold layers comprises:

forming a plurality of sacrificial patterns in the plurality of recess regions; and

oxidizing the plurality of sacrificial patterns to form the plurality of third mold layers, wherein each of the plurality of third mold layers is in contact with a corresponding recessed first mold layer of the plurality of recessed first mold layers.

6. The method of claim 1,

wherein the forming of the plurality of third mold layers comprises:

forming a sacrificial layer along an inner side surface of the hole to fill the plurality of recessed regions;

etching the sacrificial layer to expose side surfaces of the plurality of second mold layers, thereby forming a plurality of sacrificial patterns remaining in the plurality of recess regions; and

oxidizing the plurality of sacrificial patterns to form the plurality of third mold layers.

7. The method of claim 6,

wherein the sacrificial layer is formed of a semiconductor material.

8. The method of claim 1,

wherein a side surface of each of the plurality of third mold layers exposed by the hole has a rounded shape.

9. The method of claim 1, further comprising:

sequentially forming the plurality of information storage patterns on the first dielectric layer, a second dielectric layer to cover the first dielectric layer and the plurality of information storage patterns, and a channel semiconductor layer on the second dielectric layer so that the second dielectric layer is interposed between the first dielectric layer and the semiconductor channel layer and between the plurality of information storage patterns and the semiconductor channel layer in the hole.

10. The method of claim 1, further comprising:

forming a separation trench passing through the plurality of interlayer insulation layers and the plurality of second mold layers;

removing the plurality of second mold layers exposed by the separation trench to form a plurality of void spaces;

forming a plurality of gate patterns in the plurality of void spaces; and

forming a separation structure in the separation trench.

11. A method of manufacturing a semiconductor device comprising:

forming a stacked structure including a plurality of preliminary first mold layers and a plurality of preliminary second mold layers alternately and repeatedly stacked on a lower structure in a vertical direction, perpendicular to the lower structure;

forming a hole passing through the stacked structure to form a plurality of first mold layers and a plurality of second mold layers, the hole exposing side surfaces of the plurality of first mold layers and side surfaces of the plurality of second mold layers;

etching partially the plurality of first mold layers exposed by the holes to form a plurality of recess regions and a plurality of recessed first mold layers;

forming a plurality of third mold layers in the plurality of recess regions to form a plurality of interlayer insulation layers, each of the plurality of interlayer insulation layers including a corresponding recessed first mold layer of the plurality of recessed first mold layers and a corresponding third mold layer of the plurality of third mold layers that are positioned at the same level in the vertical direction,

wherein each of the plurality of third mold layers is interposed between two adjacent second mold layers of the plurality of second mold layers and is protruded into the hole beyond side surfaces of the two adjacent second mold layers;

forming a first dielectric layer in the hole along side surfaces of the plurality of third mold layers and the side surfaces of the plurality of second mold layers;

forming a plurality of information storage patterns on the first dielectric layer, the plurality of information storage patterns being opposite to the plurality of second mold layers and spaced apart from each other in the vertical direction;

forming a second dielectric layer covering the first dielectric layer and the plurality of information storage patterns in the hole so that the plurality of information storage patterns are interposed between the first dielectric layer and the second dielectric layer; and

forming a channel semiconductor layer covering the second dielectric layer in the hole,

wherein each of the plurality of information storage patterns has an overlapped portion overlapping the plurality of third mold layers in the vertical direction and a non-overlapped portion overlapping the plurality of third mold layers in the vertical direction.

12. The method of claim 11,

wherein the overlapped portion of each of the plurality of information storage patterns is adjacent to a corresponding one of the plurality of second mold layers, and the non-overlapped portion of each of the plurality of information storage patterns is adjacent to the second dielectric layer.

13. The method of claim 11,

wherein the overlapped portion and the non-overlapped portion have different thickness from each other.

14. The method of claim 13,

wherein the overlapped portion has a thickness greater than a thickness of the non-overlapped portion.

15. The method of claim 11,

wherein the forming of the plurality of third mold layers in the recess regions comprises:

forming a sacrificial layer on an inner wall of the hole;

etching the sacrificial layer to form a plurality of sacrificial patterns remaining in the plurality of recess regions; and

oxidizing the plurality of sacrificial patterns to form the plurality of third mold layers.

16. The method according to claim 11, further comprising:

forming a separation trench passing through the plurality of interlayer insulation layers and the plurality of second mold layers;

removing the plurality of second mold layers exposed by the separation trench to form a plurality of void spaces;

forming a plurality of gate patterns in the plurality of void spaces; and

forming a separation structure in the separation trench.

17. A method of manufacturing a semiconductor device comprising:

forming a stacked structure by alternately stacking a plurality of interlayer insulation layers and a plurality of mold layers on a substrate,

wherein a hole having a corrugated inner side surface passes through the stacked structure, and

wherein each of the plurality of interlayer insulation layers has a rounded corner as part of the corrugated inner side surface of the hole; and

forming a vertical memory structure including a plurality of information storage patterns on the corrugated inner side surface of the hole so that the plurality of information storage patterns are spaced apart from each other in a vertical direction perpendicular to the substrate,

wherein each of the plurality of interlayer insulation layers includes an inner mold layer having a first density and an outer mold layer having a second density greater than the first density.

18. The method of claim 17,

wherein the stacking of the plurality of interlayer insulation layers and the plurality of mold layers comprises:

alternately stacking a plurality of first mold layers and the plurality of mold layers on the substrate;

partially removing the plurality of first mold layers along a side surface of a first hole passing through the stacked structure to form a plurality of recess regions and a plurality of recessed first mold layers;

forming a plurality of sacrificial patterns in the plurality of recess regions; and

oxidizing the plurality of sacrificial patterns to form a plurality of third mold layers that fill the plurality of recess regions, the plurality of third mold layers extending into the first hole,

wherein each of the plurality of interlayer insulation layers includes a corresponding third mold layer of the plurality of third mold layers and a corresponding recessed first mold layer of the plurality of recessed first mold layers that are positioned at the same level in the vertical direction, and

wherein side surfaces of the plurality of third mold layers and side surfaces of the plurality of mold layers are connected to each other to form the corrugated inner side surface of the hole.

19. The method according to claim 18,

wherein the plurality of mold layers are formed of silicon oxide formed by a deposition process;

the plurality of sacrificial patterns are formed of silicon; and

the plurality of third mold layers are formed of silicon oxide formed by the oxidizing of the plurality of sacrificial patterns.

20. The method according to claim 17, further comprising:

forming a separation trench passing through the plurality of interlayer insulation layers and the plurality of mold layers;

removing the plurality of mold layers exposed by the separation trench to form a plurality of void spaces;

forming a plurality of gate patterns in the plurality of void spaces; and

forming a separation structure in the separation trench,

wherein the plurality of void spaces expose the vertical memory structure,

the vertical memory structure further includes a first dielectric layer and a second dielectric layer, and

the first dielectric layer is formed on the corrugated inner side surface of the hole, and

the plurality of information storage patterns are disposed between the first dielectric layer and the second dielectric layer.