MONOLITHIC INTEGRATION OF GAN HEMT AND SI CMOS
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Abstract
A CMOS process is disclosed for manufacturing an integrated circuit including both MOSFETS and GaN HEMT devices. Each GaN HEMT device resides within an oxidized window that exposes a silicon substrate having a <111> crystal lattice orientation.
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Citations
21 Claims
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1-9. -9. (canceled)
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10. An integrated circuit, comprising:
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a silicon handle substrate having a <
111>
crystal lattice orientation;a silicon device layer configured to include a plurality of metal-oxide field effect transistors (MOSFETs); a buried oxide layer separating the silicon handle substrate from the silicon device layer; a plurality of shallow trench isolation (STI regions configured to isolate the plurality of MOSFETs, wherein one of the STI regions includes a window extending through the buried oxide layer to the silicon handle substrate; a gallium nitride high electron mobility transistor (GaN HEMT) within the window comprising; a pair of aluminum-based source/drain contacts; an aluminum-based gate; a nucleation layer contacting the silicon handle substrate; a buffer layer contacting the nucleation layer; a gallium nitride (GaN) channel layer contacting the buffer layer; a barrier layer contacting the GaN channel layer; and a cap layer contacting the barrier layer, wherein the pair of aluminum-based source/drain contacts and the aluminum-based gate are all coupled to the GaN HEMT through the cap layer. - View Dependent Claims (12, 13, 15, 16, 17, 18, 19, 20)
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11. (canceled)
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14. (canceled)
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21-27. -27. (canceled)
Specification