MONOLITHIC INTEGRATION OF GAN HEMT AND SI CMOS
A CMOS process is disclosed for manufacturing an integrated circuit including both MOSFETS and GaN HEMT devices. Each GaN HEMT device resides within an oxidized window that exposes a silicon substrate having a <111> crystal lattice orientation.
- 1-9. -9. (canceled)
- 10. An integrated circuit, comprising:
a silicon handle substrate having a <
crystal lattice orientation;
a silicon device layer configured to include a plurality of metal-oxide field effect transistors (MOSFETs); a buried oxide layer separating the silicon handle substrate from the silicon device layer; a plurality of shallow trench isolation (STI regions configured to isolate the plurality of MOSFETs, wherein one of the STI regions includes a window extending through the buried oxide layer to the silicon handle substrate; a gallium nitride high electron mobility transistor (GaN HEMT) within the window comprising; a pair of aluminum-based source/drain contacts; an aluminum-based gate; a nucleation layer contacting the silicon handle substrate; a buffer layer contacting the nucleation layer; a gallium nitride (GaN) channel layer contacting the buffer layer; a barrier layer contacting the GaN channel layer; and a cap layer contacting the barrier layer, wherein the pair of aluminum-based source/drain contacts and the aluminum-based gate are all coupled to the GaN HEMT through the cap layer.
- View Dependent Claims (12, 13, 15, 16, 17, 18, 19, 20)
- 11. (canceled)
- 14. (canceled)
- 21-27. -27. (canceled)
This application relates to integrated circuits, and more particularly to the monolithic integration of GaN HEMT and Si CMOS.
Complementary metal-oxide semiconductor (CMOS) technology is now quite mature such that digital circuits incorporating millions of transistors are readily integrated into ever-shrinking footprints on a silicon substrate. But mobile devices such as smartphones also require assorted radio frequency (RF) analog components such as power amplifiers and filters. III-V devices such as GaN high electron mobility transistors (HEMTs) offer superior RF performance for such RF analog components but are generally incompatible with CMOS processing. These non-CMOS analog components are thus typically fabricated individually and then integrated with the remaining system on a circuit board to complete the RF frontend (RFFE) of a smartphone or other wireless device. But the circuit board integration of such discrete components leads to substantial parasitic losses at higher frequencies such as in fifth-generation (5G) frequency bands. In addition, the fabrication of individual components and resulting circuit board integration increases manufacturing costs and complexity.
Accordingly, there is a need in the art for the monolithic integration of GaN HEMT with silicon CMOS.
Various integrated circuit are disclosed that include both silicon-based MOSFETs and GaN high electron mobility transistor (HEMT) devices that are formed using a CMOS process. In one embodiment, a silicon device layer for a silicon-on-insulator (SOI) wafer includes the silicon-based MOSFETs. The MOSFETS are insulated by shallow trench isolation (STI) regions. A window etched through one of the STI regions and through the buried oxide layer for the SOI wafer exposes a portion of the silicon handle substrate. In contrast to the <100> crystal lattice orientation for the silicon device layer, the silicon handle substrate has a <111> crystal lattice orientation. The <111> orientation provides reduced lattice mismatch to a GaN high electron mobility transistor (HEMT) epitaxially deposited onto the exposed portion of the silicon handle substrate to fill the window. A CMOS back-end-of-line (BEOL) process completes the integrate circuit. In some embodiments, the resulting integrated circuit is wafer bonded such as through a layer-transfer process to another silicon wafer containing additional MOSFETs.
In a non-SOI embodiment, a <111> silicon wafer is oxidized to include an oxidized layer. In contrast to the SOI embodiment, there is thus no silicon device layer for the non-SOI embodiment. But the CMOS manufacture process for the non-SOI embodiment is analogous in that a window for each GaN HEMT transistor is etched through the oxidized layer to expose a corresponding portion of the <111> silicon wafer. A GaN HEMT is epitaxially deposited to fill each window. A CMOS BEOL process completes processing of the <111> silicon wafer, which is then wafer bonded such as through a layer-transfer process to another silicon wafer containing MOSFETs.
These and other advantageous features may be better appreciated through the following detailed description.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.
At least one GaN HEMT is monolithically integrated onto a silicon-on-insulator (SOI) substrate. The SOI substrate may include CMOS metal-oxide field effect transistors (MOSFET). In this fashion, low cost and mature CMOS processing technology is leveraged to produce an integrated circuit containing both Si CMOS and GaN HEMT devices. Turning now to the drawings, an example integrated circuit 100 is formed on a silicon-on-insulator (SOI) wafer 101. But in contrast to conventional CMOS SOI architectures, a silicon handle substrate 105 for wafer 101 has a <111> crystal lattice orientation as opposed to a <100> orientation. As will be explained further herein, such a crystal lattice orientation presents a minimal lattice mismatch to a GaN HEMT 110 integrated onto wafer 101. Silicon-on-insulator wafer 101 is a 300 mm wafer in the following description although it will be appreciated that the wafer size may vary in alternative embodiments.
SOI substrate 101 includes a buried oxide (BOX) layer 140 that insulates silicon handle substrate 105 from a device silicon layer 160 having a conventional <100> crystal lattice orientation. Device silicon layer 160 is patterned and doped to form a plurality of CMOS-process MOSFETs 145 that are isolated by shallow trench isolation (STI) regions 165. As illustrated, MOSFETS 145 are n-type metal-oxide semiconductor (NMOS) MOSFETs but it will be appreciated that device silicon layer 160 may readily be patterned and doped to also support p-type metal-oxide semiconductor (PMOS) devices as well. A window 180 through device layer 160 and box layer 140 is filled by a GaN HEMT 110 device. STI regions 165 border window 180 so that GaN HEMT 110 is isolated from MOSFETs 145. It will be appreciated that SOI wafer 101 may include a plurality of such windows 180 to support a corresponding plurality of GaN HEMT devices. GaN HEMT 110 includes an aluminum nitride (AlN) nucleation layer 115 contacting an exposed portion of silicon handle substrate 105 within window 180. Nucleation layer 115 is separated from a gallium nitride (GaN) channel 125 by a graded aluminum gallium nitride (AlGaN) buffer layer 120. An AlGaN barrier layer 130 separates GaN channel 125 from a GaN cap layer 135. Source/drain contacts 185 and a gate 190 contact GaN cap layer 135. Note that it would be conventional in a III-V process to form source/drain contacts 185 and gate 190 using gold. But such III-V gold processing steps are not compatible with the CMOS process used to construct integrated circuit 100. Suitable CMOS-compatible contact materials are aluminum based. For example, gate 190 may be formed using nickel aluminum tantalum (NiAlTa) whereas contacts 185 may be formed of titanium aluminum tantalum (TiAlTa).
A conventional back-end-of the-line (BEOL) process may be used to complete integrated circuit 100. For illustration clarity, integrated circuit 100 is shown having just a first metal layer M1 and a second metal layer M2 as insulated by corresponding dielectric layers 175 but it will be appreciated that additional metal layers may be implemented in integrated circuit 100 using conventional BEOL processes. MOSFETs 145 are coupled to GaN HEMT 110 through vias 150 extending through the dielectric layers to leads formed in the metal layers. Integrated circuit 100 connects to additional integrated circuits or other remote devices through terminals (not illustrated) such as copper pillars or solder balls. Integrated circuit 100 may be advantageously constructed in a CMOS fabrication facility or foundry without requiring any separate processing by a III-V foundry. Suitable applications such as the RF frontend of a smartphone may thus be constructed using integrated circuit 100 as opposed to the conventional use of multiple integrated circuits, which significantly lowers cost and complexity. Moreover, the RF performance and fidelity are greatly enhanced as the parasitic resistance, capacitance, and inductance for the signal coupling between MOSFETs 145 and GaN HEMT 110 in integrated circuit 100 are advantageously lowered as compared to the parasitic resistance, capacitance, and inductance introduced by the circuit board coupling of discrete integrated circuits. A CMOS-compatible method of manufacturing integrated circuit 100 will now be discussed.
The manufacture begins with a silicon-on-insulator (SOI) substrate or wafer 101 as shown in
To begin the formation of a GaN high electron mobility transistor, a window 180 is etched through one of the shallow trench isolation regions 165 and through buried oxide layer 140 to expose silicon handle layer 105 as shown in
With window 180 completed, the CMOS foundry may proceed to epitaxially deposit layers for GaN HEMT 110 within window 180 as shown in
To complete GaN HEMT 110, source/drain contacts 185 and gate 190 are deposited as shown in
In an alternative embodiment, the processing steps discussed with regard to
Wafer 101 as discussed with reference to
A method of manufacturing an integrated circuit having both CMOS devices and GaN HEMT devices using a CMOS process will now be discussed with reference to the flowchart of
It will be appreciated that many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.