MONOLITHIC INTEGRATION OF GAN HEMT AND SI CMOS

• US 20200135766A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Dutta, Ranadeep, Goktepeli, Sinan, Scuderi, Antonino, Imthurn, George Pete
• Application Number:
  US16/175,691
• Publication Number:
  US 20200135766A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/454 on thin film AIII-BV compounds
• CPC Class Codes: H01L 29/475 on AIII-BV compounds
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A CMOS process is disclosed for manufacturing an integrated circuit including both MOSFETS and GaN HEMT devices. Each GaN HEMT device resides within an oxidized window that exposes a silicon substrate having a <111> crystal lattice orientation.

Claims

1-9. -9. (canceled)

10. An integrated circuit, comprising:

a silicon handle substrate having a <

111>

crystal lattice orientation;

a silicon device layer configured to include a plurality of metal-oxide field effect transistors (MOSFETs);

a buried oxide layer separating the silicon handle substrate from the silicon device layer;

a plurality of shallow trench isolation (STI regions configured to isolate the plurality of MOSFETs, wherein one of the STI regions includes a window extending through the buried oxide layer to the silicon handle substrate;

a gallium nitride high electron mobility transistor (GaN HEMT) within the window comprising;

a pair of aluminum-based source/drain contacts;

an aluminum-based gate;

a nucleation layer contacting the silicon handle substrate;

a buffer layer contacting the nucleation layer;

a gallium nitride (GaN) channel layer contacting the buffer layer;

a barrier layer contacting the GaN channel layer; and

a cap layer contacting the barrier layer, wherein the pair of aluminum-based source/drain contacts and the aluminum-based gate are all coupled to the GaN HEMT through the cap layer.

12. The integrated circuit of claim 10, wherein the pair of aluminum-based source/drain contacts comprise a pair of titanium aluminum tantalum (TiAlTa) source/drain contacts.

13. The integrated circuit of claim 10, wherein the aluminum-based gate comprises a T-shaped nickel aluminum tantalum (NiAlTa) gate.

15. The integrated circuit of claim 10, wherein the nucleation layer comprises aluminum nitride (AlN).

16. The integrated circuit of claim 10, wherein the buffer layer comprises aluminum gallium nitride (AlGaN).

17. The integrated circuit of claim 10, wherein the barrier layer comprises AlGaN.

18. The integrated circuit of claim 10, wherein the barrier layer comprises lattice-matched indium aluminum nitride (InAlN).

19. The integrated circuit of claim 10, wherein the cap layer comprises GaN.

20. The integrated circuit of claim 10, further comprising:

an additional integrated circuit wafer bonded to the integrated circuit, wherein the additional integrated circuit includes an additional plurality of MOSFETs.

11. (canceled)

14. (canceled)

21-27. -27. (canceled)