METHOD FOR FABRICATING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY

• US 20200135767A1
• Filed: 11/29/2018
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: HKC Corporation Limited (Shenzhen Huike Investment Holding Co., Ltd.)
• Original Assignee: HKC Corporation Limited (Shenzhen Huike Investment Holding Co., Ltd.)
• Inventors: Ge, Bangtong, Fu, Tingting
• Granted Patent: US 10,727,256 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/103 a-Si
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method for fabricating an array substrate, after the wet etching process of the source-drain metal layer (17), performs first ashing for the island-like photoresist pattern (19), such that the edge of the island-like photoresist pattern (19) is aligned with the edge of the source-drain metal segment (171).

Claims

1. A method for fabricating an array substrate, comprising:

providing a substrate base layer, forming a gate electrode on the substrate base layer, and forming a gate insulating layer on the gate electrode and the substrate base layer;

sequentially forming a semiconductor material layer and a source-drain metal layer on the gate insulating layer, and forming an island-like photoresist pattern on the source-drain metal layer, wherein the island-like photoresist pattern comprises a first portion and a second portion disposed on both sides of the first portion, and the height of the second portion is greater than the height of the first portion;

wherein the source-drain metal layer is first wet etched by using the island-like photoresist pattern as a mask. so as to obtain a source-drain metal segment;

performing first ashing, for the island-like photoresist pattern, such that the edge of the island-like photoresist pattern is aligned with the edge of the source-drain metal segment;

performing first dry etching for the semiconductor material layer by using the photoresist pattern after first ashing as a mask, so as to obtain an active segment portion;

performing second ashing for the island-like photoresist pattern after first ashing, so as to remove the first portion, and obtain third portions disposed at intervals, wherein the height of the third portions are less than the height of the first portion; and

performing second wet etching for the source-drain metal segment by using the third portions as a mask, so as to obtain a source electrode and a drain electrode.

2. The method according to claim 1, wherein the semiconductor material layer comprises an amorphous silicon layer and a doped layer formed on the amorphous silicon layer;

and the active segment portion comprises an amorphous silicon segment and a doped segment disposed on the amorphous silicon segment.

3. The method according to claim 2, wherein the doped layer is an amorphous silicon layer doped with an n-type element.

4. The method according to claim 2, wherein the amorphous silicon layer has a thickness of 1000 to 4000 angstroms, and the doped layer has a thickness of 300 to 1000 angstroms.

5. The method according to claim 2, wherein, after obtaining the source electrode and the drain electrode, the method further comprises performing second dry etching for the doped segment, so as to obtain an ohmic contact layer disposed on both sides of the amorphous silicon segment.

6. The method according to claim 2, wherein the amorphous silicon layer is deposited on the gate insulating layer by chemical vapor deposition, and the doped layer is deposited on the gate insulating layer by chemical vapor deposition.

7. The method according to claim 1, wherein the first dry etching further comprises a method for increasing a ratio of rates of longitudinal etching and lateral etching.

8. The method according to claim 7, wherein the method for increasing a ratio of rates of longitudinal etching and lateral etching comprises at least one of the following steps:

reducing a ratio of a flow rate of an etching reaction gas;

improving an etching power; and

reducing etching gas pressure, and reducing concentration of reaction gas in an etching chamber.

9. The method according to claim 1, wherein the first ashing uses a mixed gas of oxygen and a fluorine-containing gas;

and the fluorine-containing gas comprises at least one of NF3, CF4, C2F6, C4F8, CHF3, and SF6.

10. The method according to claim 1, wherein the second ashing uses a mixed gas of oxygen and a fluorine-containing gas;

and the fluorine-containing gas comprises at least one of NF3, CF4, C2F6, C4F8, CHF3, and SF6.

11. The method according to claim 1, wherein the material of the source-drain metal layer is at least one of chromium, molybdenum, copper, titanium, aluminum or molybdenum nitride.

12. The method according to claim 11, wherein the source-drain metal layer is a Mo/Al/Mo layer, a MoN/AL/Mo layer, or a Mo/Al/MoN layer.

13. The method according to claim 12, wherein the upper Mo layer or MoN layer has a thickness of 100-500 angstroms, the middle Al layer has a thickness of 2000-5500 angstroms, and the lower Mo layer or MoN layer has a thickness of 100-300 angstroms.

14. The method according to claim 13, wherein the time for the second wet etching does not exceed 150 seconds.

15. The method according to claim 1, wherein, after the first wet etching, the edge of the source-drain metal segment is inwardly indented by a distance of 0.5-1.5 μ

m with respect to the edge of the island-like photoresist pattern.

16. The method according to claim 1, wherein, after the second wet etching, the source electrode and the drain electrode obtained are inwardly indented by a distance of 0.5-1.5 μ

m with respect to the edge of the third portions.

17. An array substrate, comprising an amorphous silicon segment, wherein a tail made of amorphous silicon of the amorphous silicon segment has a length of 1-1.6 μ

m.

18. The array substrate according to claim 17, wherein the array substrate further comprises an ohmic contact layer disposed on both sides of the amorphous silicon segment and disposed between a source electrode and a drain electrode, wherein the ohmic contact layer protrudes from the edges of the source electrode and the drain electrode by a length of 0.1 and 0.4 μ

m.

19. A display, comprising an array substrate, wherein the array substrate comprises a an amorphous silicon segment, and a source electrode and a drain electrode disposed on both sides of the amorphous silicon segment, wherein a tail made of amorphous silicon of the amorphous silicon segment has a length of 1-1.6 μ

m, the source electrode and the drain electrode are a Mo/Al/Mo layer, a MoN/Al/Mo layer, or a Mo/Al/MoN layer, and the upper Mo layer or MoN layer has a thickness of 100-500 angstroms, the middle Al layer has a thickness of 2000-5500 angstroms, and the lower Mo layer or MoN layer has a thickness of 100-300 angstroms.

20. The display according to claim 19, wherein the array substrate further comprises an ohmic contact layer disposed on both sides of the amorphous silicon segment and disposed between a source electrode and a drain electrode, wherein the ohmic contact layer protrudes from the edges of the source electrode and the drain electrode by a length of 0.1 and 0.4 μ

m.