SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20200135768A1
• Filed: 03/13/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HUNG, Tsung-Yu, LEE, Pei-Wei, TSAI, Pang-Yen
• Granted Patent: US 10,872,906 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02516 Crystal orientation
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor device includes a substrate, a first semiconductor fin and a gate stack. The first semiconductor fin is over the substrate and includes a first germanium-containing layer and a second germanium-containing layer over the first germanium-containing layer. The first germanium-containing layer has a germanium atomic percentage higher than a germanium atomic percentage of the second germanium-containing layer. The gate stack is across the first semiconductor fin.

Claims

1. A semiconductor device, comprising:

a substrate;

a first semiconductor fin over the substrate and comprising a first germanium-containing layer and a second germanium-containing layer over the first germanium-containing layer, wherein the first germanium-containing layer has a germanium atomic percentage higher than a germanium atomic percentage of the second germanium-containing layer; and

a gate stack across the first semiconductor fin.

2. The semiconductor device of claim 1, wherein the first semiconductor fin further comprises a third germanium-containing layer under the first germanium-containing layer and having a germanium atomic percentage lower than the germanium atomic percentage of the first germanium-containing layer.

3. The semiconductor device of claim 2, wherein a germanium atomic percentage difference between the first and second germanium-containing layers is greater than a germanium atomic percentage difference between the second and third germanium-containing layers.

4. The semiconductor device of claim 2, wherein a germanium atomic percentage difference between the first and third germanium-containing layers is greater than a germanium atomic percentage difference between the second and third germanium-containing layers.

5. The semiconductor device of claim 2, wherein the germanium atomic percentage of the second germanium-containing layer is substantially the same as the germanium atomic percentage of the third germanium-containing layer.

6. The semiconductor device of claim 2, wherein an interface between the first and third germanium-containing layers is on a (111) plane.

7. The semiconductor device of claim 1, wherein an interface between the first and second germanium-containing layers is on a (111) plane.

8. The semiconductor device of claim 1, further comprising:

a second semiconductor fin over the substrate, wherein the second semiconductor fin has a top end in a position higher than a top end of an interface between the first and second germanium-containing layers.

9. The semiconductor device of claim 8, further comprising:

a dielectric layer between the second semiconductor fin and the substrate.

10. The semiconductor device of claim 9, wherein an interface between the dielectric layer and the second semiconductor fin is in a position lower than a bottom end of the interface between the first and second germanium-containing layers.

11. A semiconductor device, comprising:

a substrate;

a first semiconductor fin protruding above the substrate, the first semiconductor fin comprising a first germanium-containing layer and a second germanium-containing layer having a germanium atomic percentage lower than a germanium atomic percentage of the first germanium-containing layer; and

a p-type epitaxy region across the first semiconductor fin, the second germanium-containing layer being between the p-type epitaxy region and the first germanium-containing layer.

12. The semiconductor device of claim 11, further comprising:

a second semiconductor fin protruding above the substrate and having a germanium atomic percentage lower than the germanium atomic percentage of the first germanium-containing layer of the first semiconductor fin.

13. The semiconductor device of claim 12, wherein the germanium atomic percentage of the second semiconductor fin is substantially the same as the germanium atomic percentage of the second germanium-containing layer of the first semiconductor fin.

14. The semiconductor device of claim 12, further comprising:

a third semiconductor fin protruding above the substrate and free of germanium.

15. The semiconductor device of claim 11, wherein the p-type epitaxy region is interfaced with the first and second germanium-containing layers.

16. The semiconductor device of claim 11, wherein the first semiconductor fin further comprises a third germanium-containing layer between the first germanium-containing layer and the substrate, and the third germanium-containing layer has a germanium atomic percentage lower than the germanium atomic percentage of the first germanium-containing layer.

17. The semiconductor device of claim 16, wherein the germanium atomic percentage of the second germanium-containing layer is substantially the same as the germanium atomic percentage of the third germanium-containing layer.

18. A method, comprising:

etching a hybrid substrate to form a recess extending into the hybrid substrate, wherein the hybrid substrate comprises a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation, wherein after the etching, a top surface of the first semiconductor layer is exposed to the recess;

forming a spacer on a sidewall of the recess;

performing a first epitaxy process to grow a first germanium-containing layer from the exposed top surface of the first semiconductor layer;

performing a second epitaxy process to grow a second germanium-containing layer from the first germanium-containing layer, wherein a flow rate of a germanium-containing gas used in the second epitaxy process is less than a flow rate of a germanium-containing gas used in the first epitaxy process; and

patterning the first and second germanium-containing layers to form a fin.

19. The method of claim 18, wherein the first epitaxy process is performed such that the first germanium-containing layer comprises a first portion grown from the first semiconductor layer and a second portion grown from a facet of the first portion, the facet is on a (111) plane, and the second portion has a germanium atomic percentage higher than a germanium atomic percentage of the first portion.

20. The method of claim 19, wherein the second epitaxy process is performed such that at least a portion of the second germanium-containing layer is grown from the second portion.