DISPLAY DEVICE COMPRISING A PLURALITY OF THIN FILM TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME

• US 20200135772A1
• Filed: 10/23/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: LEE, Seungmin
• Granted Patent: US 11,177,288 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: G02F 2202/104 poly-Si
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66969 : of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78633 : with a light shield
• CPC Class Codes: H01L 29/78675 : with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1201 : Manufacture or treatment
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 : Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 : Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/131 : Interconnections, e.g. wiring lines or terminals

Abstract

A display device can include a pixel driver disposed on a substrate; and a display element electrically connected with the pixel driver, in which the pixel driver includes a first thin film including a first semiconductor layer, a first gate electrode, at least a part of the first gate electrode overlapping with the first semiconductor layer, and a first source electrode and a first drain electrode respectively connected with the first semiconductor layer; and a second thin film including a second semiconductor layer, a second gate electrode, at least a part of the second gate electrode overlapping with the second semiconductor layer, and a second source electrode and a second drain electrode respectively connected with the second semiconductor layer, in which the first semiconductor layer and the second semiconductor layer are disposed in different layers, and the first source electrode, the first drain electrode, the second gate electrode, the second source electrode, and the second drain electrode are disposed in a same layer.

Claims

1. A display device comprising:

a pixel driver disposed on a substrate; and

a display element electrically connected with the pixel driver,

wherein the pixel driver includes a first thin film transistor and a second thin film transistor,

wherein the first thin film transistor includes;

a first semiconductor layer;

a first gate electrode, at least a part of the first gate electrode overlapping with the first semiconductor layer; and

a first source electrode and a first drain electrode respectively connected with the first semiconductor layer, and

wherein the second thin film transistor includes;

a second semiconductor layer;

a second gate electrode, at least a part of the second gate electrode overlapping with the second semiconductor layer; and

a second source electrode and a second drain electrode respectively connected with the second semiconductor layer,

wherein the first semiconductor layer and the second semiconductor layer are disposed in different layers, and

wherein the first source electrode, the first drain electrode, the second gate electrode, the second source electrode, and the second drain electrode are disposed in a same layer.

2. The display device according to claim 1, wherein the first semiconductor layer includes a polysilicon semiconductor layer, and

wherein the second semiconductor layer includes an oxide semiconductor layer.

3. The display device according to claim 1, further comprising:

a first gate insulating film disposed between the first semiconductor layer and the first gate electrode; and

a second gate insulating film disposed on the second semiconductor layer,

wherein the first source electrode, the first drain electrode, the second gate electrode, the second source electrode, and the second drain electrode are disposed on the second gate insulating film.

4. The display device according to claim 3, wherein a first pattern portion of the second gate insulating film disposed below the first source electrode has a pattern shape corresponding to the first source electrode,

wherein a second pattern portion of the second gate insulating film disposed below the first drain electrode has a pattern shape corresponding to the first drain electrode,

wherein a third pattern portion of the second gate insulating film disposed below the second source electrode has a pattern shape corresponding to the second source electrode, and

wherein a fourth pattern portion of the second gate insulating film disposed below the second drain electrode has a pattern shape corresponding to the second drain electrode.

5. The display device according to claim 1, wherein any one of the first drain electrode and the first source electrode is formed as one body with the second gate electrode.

6. The display device according to claim 1, further comprising:

a first conduction plate disposed between the substrate and the first semiconductor layer; and

a second conduction plate disposed between the substrate and the second semiconductor layer,

wherein the first conduction plate and the second conduction plate are spaced apart from each other, and

wherein at least a part of the first conduction plate overlaps with at least a part of the second conduction plate.

7. The display device according to claim 6, wherein the first conduction plate and the second conduction plate are disposed closer to the substrate than both of the first semiconductor layer and the second semiconductor layer.

8. The display device according to claim 6, wherein any one of the first conduction plate and the second conduction plate is connected with the first thin film transistor, and the other one of the first conduction plate and the second conduction plate is connected with the second thin film transistor.

9. The display device according to claim 6, wherein a portion of the first conduction plate overlapping with the first semiconductor layer is a first light shielding layer for blocking light being incident on the first semiconductor layer from outside of the display device, and

wherein a portion of the second conduction plate overlapping with the second semiconductor layer is a second light shielding layer for blocking light being incident on the second semiconductor layer from outside of the display device.

10. The display device according to claim 1, further comprising:

a data line configured to supply a data voltage to the pixel driver,

wherein the first thin film transistor is a switching transistor configured to control the data voltage.

11. The display device according to claim 1, further comprising:

a driving power line configured to supply a driving voltage to the display element,

wherein the second thin film transistor is a driving transistor configured to control the driving voltage.

12. The display device according to claim 1, further comprising:

a shift register disposed on the substrate and electrically connected with the pixel driver,

wherein the shift register includes a stage connected with a pixel through a gate line,

wherein the stage includes at least one stage thin film transistor, and

wherein the stage thin film transistor is disposed in a same layer as the first thin film transistor.

13. The display device according to claim 12, wherein the stage thin film transistor includes a polysilicon semiconductor layer.

14. The display device according to claim 12, wherein the stage includes an inverter, and

wherein the inverter includes a thin film transistor having a same configuration as the first thin film transistor and another thin film transistor having a same configuration as the second thin film transistor.

15. An inverter comprising:

a first thin film transistor including;

a first semiconductor layer,

a first gate electrode, at least a part of the first gate electrode overlapping with the first semiconductor layer, and

a first source electrode and a first drain electrode respectively connected with the first semiconductor layer; and

a second thin film transistor including;

a second semiconductor layer,

a second gate electrode, at least a part of the second gate electrode overlapping with the second semiconductor layer, and

a second source electrode and a second drain electrode respectively connected with the second semiconductor layer,

wherein the first semiconductor layer and the second semiconductor layer are disposed in different layers,

wherein the first source electrode, the first drain electrode, the second gate electrode, the second source electrode, and the second drain electrode are disposed in a same layer, and

wherein any one of the first source electrode and the first drain electrode is connected with any one of the second source electrode and the second drain electrode.

16. The inverter according to claim 15, wherein any one of the first source electrode and the first drain electrode is formed as one body with any one of the second source electrode and the second drain electrode.

17. The inverter according to claim 15, wherein the first semiconductor layer includes a polysilicon semiconductor layer, and

wherein the second semiconductor layer includes an oxide semiconductor layer.

18. The inverter according to claim 15, further comprising:

a first gate insulating film disposed between the first gate electrode and the first semiconductor layer; and

a second gate insulating film disposed on the second semiconductor layer,

wherein the first source electrode, the first drain electrode, the second gate electrode, the second source electrode, and the second drain electrode are disposed on the second gate insulating film.

19. The inverter according to claim 15, wherein a first pattern portion of the second gate insulating film disposed below the first source electrode has a pattern shape corresponding to the first source electrode,

wherein a second pattern portion of the second gate insulating film disposed below the first drain electrode has a pattern shape corresponding to the first drain electrode,

wherein a third pattern portion of the second gate insulating film disposed below the second source electrode has a pattern shape corresponding to the second source electrode, and

wherein a fourth pattern portion of the second gate insulating film below the second drain electrode has a pattern shape corresponding to the second drain electrode.

20. The inverter according to claim 15, wherein the first thin film transistor is a P-type transistor, and the second thin film transistor is an N-type transistor.