INVERTER CIRCUIT STRUCTURE, GATE DRIVING CIRCUIT AND DISPLAY PANEL

• US 20200135774A1
• Filed: 12/24/2019
• Published: 04/30/2020
• Est. Priority Date: 04/29/2019
• Status: Active Grant

• Current Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Original Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Inventors: LI, Jieliang, Xu, Yuping
• Granted Patent: US 11,508,761 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

Provided are an inverter circuit structure, a gate driving circuit and a display panel. The inverter circuit structure includes a PMOS transistor and an NMOS transistor, and further includes a first active layer, a gate layer, a second active layer, a first insulating layer between the gate layer and the first active layer, and a second insulating layer between the gate layer and the second active layer. An orthographic projection of the gate on the first active layer is a first region, and a portion of the first active layer in the first region has substantially a same thickness. An orthographic projection of the gate on the second active layer is a second region, and a portion of the second active layer in the second region has substantially a same thickness.

Claims

1. An inverter circuit structure, comprising:

a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor, wherein the inverter circuit structure comprises;

a first active layer, a gate layer, a second active layer, a first insulating layer and a second insulating layer, wherein the first active layer, the gate layer and the second active layer are sequentially stacked, the first insulating layer is between the gate layer and the first active layer, and the second insulating layer is between the gate layer and the second active layer;

wherein the gate layer comprises a patterned gate, which is electrically connected to a control input terminal;

wherein an orthographic projection of the gate on the first active layer is a first region, and the first active layer has substantially a same thickness in the first region; and

an orthographic projection of the gate on the second active layer is a second region, and the second active layer has substantially a same thickness in the second region; and

wherein a first electrode of the PMOS transistor is electrically connected to a first voltage input terminal, and a second electrode of the PMOS transistor is electrically connected to an output terminal; and

a first electrode of the NMOS transistor is electrically connected to a second voltage input terminal, and a second electrode of the NMOS transistor is electrically connected to the output terminal.

2. The inverter circuit structure of claim 1, wherein the patterned gate comprises at least two strip-shaped sub-gates, wherein the at least two strip-shaped sub-gates are electrically connected to each other through at least one common terminal.

3. The inverter circuit structure of claim 2, wherein in a first direction, the second electrode of the PMOS transistor and the second electrode of the NMOS transistor are disposed between two of the at least two strip-shaped sub-gates, wherein the first direction is perpendicular to an extending direction of the at least two strip-shaped sub-gates.

4. The inverter circuit structure of claim 3, wherein the second electrode of the PMOS transistor is reused as the second electrode of the NMOS transistor, the second electrode of the NMOS transistor is electrically connected to the second active layer, and the second electrode of the NMOS transistor is electrically connected to the first active layer through a via of the second active layer, the second insulating layer and the first insulating layer in sequence.

5. The inverter circuit structure of claim 3, wherein the second electrode of the NMOS transistor is reused as the second electrode of the PMOS transistor, the second electrode of the PMOS transistor is electrically connected to the first active layer, and the second electrode of the PMOS transistor is electrically connected to the second active layer through a via of the first active layer, the first insulating layer and the second insulating layer in sequence.

6. The inverter circuit structure of claim 2, wherein the at least two strip-shaped sub-gates form a ring-shaped pattern.

7. The inverter circuit structure of claim 6, wherein an outer edge of the ring-shaped pattern is quadrilateral.

8. The inverter circuit structure of claim 1, wherein the first active layer comprises a polysilicon active layer, and the second active layer comprises an oxide active layer.

9. The inverter circuit structure of claim 8, further comprising:

a substrate, wherein the first active layer is disposed on a side of the gate layer facing towards the substrate; and

a third insulating layer, wherein the first electrode of the PMOS transistor, the second electrode of the PMOS transistor, the first electrode of the NMOS transistor and the second electrode of the NMOS transistor each are disposed on a side of the third insulating layer facing away from the second active layer;

wherein the first electrode of the PMOS transistor is electrically connected to the first active layer through a first via of the third insulating layer, the second insulating layer and the first insulating layer in sequence, and the second electrode of the PMOS transistor is electrically connected to the first active layer through a second via of the third insulating layer, the second insulating layer and the first insulating layer in sequence;

wherein the first electrode of the NMOS transistor is electrically connected to the second active layer through a third via of the third insulating layer, and the second electrode of the NMOS transistor is electrically connected to the second active layer through a fourth via of the third insulating layer; and

wherein the second active layer is a patterned structure, and a region where the first via is located and a region where the second via is located are exposed.

10. The inverter circuit structure of claim 9, wherein the first electrode of the PMOS transistor and the first electrode of the NMOS transistor are arranged at a same layer, and the second electrode of the PMOS transistor and the second electrode of the NMOS transistor are arranged at a same layer;

and

wherein a distance between the first electrode of the NMOS transistor and the second active layer is different from a distance between the second electrode of the NMOS transistor and the second active layer.

11. The inverter circuit structure of claim 9, wherein the first electrode of the PMOS transistor, the first electrode of the NMOS transistor, the second electrode of the PMOS transistor and the second electrode of the NMOS transistor are arranged at a same layer.

12. The inverter circuit structure of claim 8, comprising:

a substrate, wherein the second active layer is disposed on a side of the gate layer facing towards the substrate; and

a fourth insulating layer, wherein the first electrode of the PMOS transistor, the second electrode of the PMOS transistor, the first electrode of the NMOS transistor and the second electrode of the NMOS transistor each are disposed on a side of the fourth insulating layer facing away from the first active layer;

wherein the first electrode of the NMOS transistor is electrically connected to the second active layer through a fifth via of the fourth insulating layer, the first insulating layer and the second insulating layer in sequence, and the second electrode of the NMOS transistor is electrically connected to the second active layer through a sixth via of the fourth insulating layer, the first insulating layer and the second insulating layer in sequence;

wherein the first electrode of the PMOS transistor is electrically connected to the first active layer through a seventh via of the fourth insulating layer, and the second electrode of the PMOS transistor is electrically connected to the first active layer through an eighth via of the fourth insulating layer; and

wherein the first active layer has a pattered structure, and a region where the fifth via is located and a region where the sixth via is located are exposed.

13. The inverter circuit structure of claim 12, wherein the first electrode of the PMOS transistor, the first electrode of the NMOS transistor, the second electrode of the PMOS transistor and the second electrode of the NMOS transistor are arranged at a same layer.

14. The inverter circuit structure of claim 12, wherein the first electrode of the PMOS transistor and the first electrode of the NMOS transistor are arranged at a same layer, and the second electrode of the PMOS transistor and the second electrode of the NMOS transistor are arranged at a same layer;

and

wherein a distance between the first electrode of the NMOS transistor and the first active layer is different from a distance between the second electrode of the NMOS transistor and the first active layer.

15. A gate driving circuit, comprising:

at least one inverter circuit structure, wherein each of the at least one inverter circuit structure comprises;

a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor,

wherein the inverter circuit structure comprises;

a first active layer, a gate layer, a second active layer, a first insulating layer and a second insulating layer, wherein the first active layer, the gate layer and the second active layer are sequentially stacked, the first insulating layer is between the gate layer and the first active layer, and the second insulating layer is between the gate layer and the second active layer;

wherein the gate layer comprises a patterned gate, which is electrically connected to a control input terminal;

wherein an orthographic projection of the gate on the first active layer is a first region, and the first active layer has substantially a same thickness in the first region;

an orthographic projection of the gate on the second active layer is a second region, and the second active layer has substantially a same thickness in the second region; and

wherein a first electrode of the PMOS transistor is electrically connected to a first voltage input terminal, and a second electrode of the PMOS transistor is electrically connected to an output terminal; and

a first electrode of the NMOS transistor is electrically connected to a second voltage input terminal, and a second electrode of the NMOS transistor is electrically connected to the output terminal.

16. A display panel, comprising a gate driving circuit, wherein the gate driving circuit comprises at least one inverter circuit structure, wherein each of the at least one inverter circuit structure comprises:

a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor,

wherein the inverter circuit structure comprises;

a first active layer, a gate layer, a second active layer, a first insulating layer and a second insulating layer, wherein the first active layer, the gate layer and the second active layer are sequentially stacked, the first insulating layer between the gate layer and the first active layer, and the second insulating layer between the gate layer and the second active layer;

wherein the gate layer comprises a patterned gate, which is electrically connected to a control input terminal;

wherein an orthographic projection of the gate on the first active layer is a first region, and the first active layer has substantially a same thickness in the first region;

an orthographic projection of the gate on the second active layer is a second region, and the second active layer has substantially a same thickness in the second region; and

wherein a first electrode of the PMOS transistor is electrically connected to a first voltage input terminal, and a second electrode of the PMOS transistor is electrically connected to an output terminal; and

a first electrode of the NMOS transistor is electrically connected to a second voltage input terminal, and a second electrode of the NMOS transistor is electrically connected to the output terminal.