IMAGING DEVICE WITH UNIFORM PHOTOSENSITVIE REGION ARRAY

• US 20200135779A1
• Filed: 03/26/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Takahashi, Seiji
• Granted Patent: US 10,734,419 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/14605 Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

Various embodiments of the present disclosure are directed towards a pixel sensor including a first and second pair of photodetectors. The pixel sensor includes the first and second pair of photodetectors in a semiconductor substrate. The first pair of photodetectors are reflection symmetric with respect to a first line positioned at a midpoint between the first pair of photodetectors. The second pair of photodetectors are reflection symmetric with respect to a second line that intersects the first line at a center point. A first plurality of transistors overlying the semiconductor substrate laterally offset the first pair of photodetectors. A second plurality of transistors overlying the semiconductor substrate laterally offset the first plurality of transistors. The first and second pair of photodetectors are laterally between the first and second plurality of transistors. The first and second plurality of transistors are point symmetric with respect to the center point.

Claims

1. A pixel sensor, comprising:

a first pair of photodetectors in a semiconductor substrate, wherein the first pair of photodetectors are reflection symmetry with respect to a first line positioned at a midpoint between the first pair of photodetectors;

a second pair of photodetectors in the semiconductor substrate, wherein the first and second pair of photodetectors are reflection symmetric with respect to a second line, wherein the second line intersects the first line at a center point;

a first plurality of transistors disposed over the semiconductor substrate laterally offset the first pair of photodetectors; and

a second plurality of transistors disposed over the semiconductor substrate laterally offset the first plurality of transistors, wherein the first and second pair of photodetectors are laterally between the first and second plurality of transistors;

wherein the first and second plurality of transistors are point symmetric with respect to the center point.

2. The pixel sensor of claim 1, wherein the first and second plurality of transistors have second order rotational symmetry with respect to the center point.

3. The pixel sensor of claim 1, wherein the first and second pair of photodetectors have fourth order rotational symmetry with respect to the center point.

4. The pixel sensor of claim 1, wherein a center of each photodetector in the first and second pair of photodetectors is substantially equidistant from the center point.

5. The pixel sensor of claim 1, further comprising:

a plurality of transfer transistors at least partially disposed over each photodetector in the first and second pair of photodetectors, wherein a center of each transfer transistor is substantially equidistant from the center point.

6. The pixel sensor of claim 5, wherein the plurality of transfer transistors are reflection symmetric with respect to the first line.

7. The pixel sensor of claim 5, wherein the plurality of transfer transistors are reflection symmetric with respect to the second line.

8. The pixel sensor of claim 1, wherein the first plurality of transistors are configured to control the first pair of photodetectors and the second plurality of transistors are configured to control the second pair of photodetectors, wherein the first plurality of transistors are electrically coupled in parallel with the second plurality of transistors.

9. The pixel sensor of claim 1, wherein the first and second plurality of transistors comprise a reset transistor, a source follower transistor, and a select transistor, respectively.

10. The pixel sensor of claim 1, further comprising:

conductive reflectors disposed over the first and second pair of photodetectors, wherein the conductive reflectors are reflection symmetric with respect to the first line.

11. An image sensor, comprising:

a substrate having a front-side and a back-side opposite to the front-side;

a pixel region disposed within the substrate and comprising a first set of two photodetectors laterally disposed next to a second set of two photodetectors, the first and second set of two photodetectors are each configured to convert radiation that enters the substrate from the back-side into an electrical signal;

a first plurality of transistors over the front-side of the substrate laterally adjacent to the first set of two photodetectors configured to receive the electrical signal from the first set of two photodetectors;

a second plurality of transistors over the front-side of the substrate laterally adjacent to the second set of two photodetectors configured to receive the electrical signal from the second set of two photodetectors, wherein the first and second plurality of transistors are on opposite sides of the pixel region;

a deep trench isolation structure enclosing an outer perimeter of the first and second plurality of transistors extending from the back-side of the substrate to a position in the substrate; and

an interconnect structure comprising a plurality of conductive wires and vias overlying the front-side of the substrate and electrically coupled to the first and second set of two photodetectors and the first and second plurality of transistors;

wherein the first and second plurality of transistors and the interconnect structure have rotational symmetry with respect to a center point of the pixel region.

12. The image sensor of claim 11, wherein centers of each photodetector in the first and second set of two photodetectors are substantially equidistant from the center point of the pixel region.

13. The image sensor of claim 11, further comprising:

a plurality of transfer transistors over each photodetector in the first and second set of two photodetectors;

a floating diffusion node within the pixel region, wherein the plurality of transfer transistors are adjacent to the floating diffusion node, and wherein center points of the plurality of transfer transistors are spaced about evenly from a center point of the floating diffusion node.

14. The image sensor of claim 11, wherein a first conductive wire in the interconnect structure spans from a first transistor in the first plurality of transistors to a second transistor in the second plurality of transistors, wherein a mid-point of the first conductive wire is aligned with the center point of the pixel region.

15. The image sensor of claim 11, wherein the first plurality of transistors are electrically coupled in parallel with the second plurality of transistors via the interconnect structure.

16. The image sensor of claim 11, wherein the interconnect structure comprises at least two layers of conductive wires vertically offset one another, wherein each layer of conductive wires is point symmetric with respect to the center point of the pixel region.

17. The image sensor of claim 11, wherein the interconnect structure comprises a plurality of conductive wires, a plurality of conductive contacts, and a plurality of conductive vias, wherein the plurality of conductive wires, contacts, and vias have at least second order rotational symmetry with respect to the center point of the pixel region, respectively.

18. The image sensor of claim 11, wherein the first and second plurality of transistors are laterally within inner sidewalls of the deep trench isolation structure and the interconnect structure is laterally within outer sidewalls of the deep trench isolation structure.

19. A method for forming a pixel sensor, the method comprising:

forming a doped well region having a first doping type in a semiconductor substrate;

forming a plurality of photodetector collector regions having a second doping type different than the first doping type in the doped well region, wherein a center point of each photodetector collector region is substantially equidistant from a center point of the doped well region;

forming a floating diffusion node in the doped well region between the plurality of photodetector collector regions;

forming a plurality of pixel device transistors laterally offset the doped well region, wherein the plurality of pixel device transistors are point symmetric with respect to the center point of the doped well region; and

forming a plurality of transfer transistors over the plurality of photodetector collector regions, wherein the plurality of transfer transistors and the plurality of photodetector collector regions are reflection symmetric with respect to a substantially straight line intersecting the center point of the doped well region.

20. The method of claim 19, further comprising:

forming reflectors over the doped well region; and

forming an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a plurality of metal wires, and wherein the reflectors and the interconnect structure are point symmetric with respect to the center point of the doped well region.