IMAGE SENSOR PACKAGE

• US 20200135790A1
• Filed: 12/04/2019
• Published: 04/30/2020
• Est. Priority Date: 11/14/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Yong-hoon, KIM, Ji-chul, CHA, Seung-yong, KIM, Jae-choon
• Granted Patent: US 10,879,294 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16147 the bump connector connecting to a bonding area disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/345 Arrangements for heating thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 27/14621 : Colour filter arrangements
• CPC Class Codes: H01L 27/14627 : Microlenses
• CPC Class Codes: H01L 27/14634 : Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 : Interconnect structures
• CPC Class Codes: H01L 27/14645 : Colour imagers
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16151 : Cap comprising an aperture, e.g. for pressure control, encapsulation
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

Claims

1. A package, comprising:

a first chip having an interconnection structure to which signals are provided;

a second chip vertically overlapping the first chip, the second chip to process the signals transmitted by the first chip, the second chip configured to generate a signal information by processing at least one of signals received from the first chip;

a third chip vertically overlapping the first and second chips, the second chip being interposed between the first chip and the third chip, the third chip configured to store the signal information received from the second chip;

a conductive pad between the first chip and the second chip, the conductive pad electrically connecting the first chip and the second chip; and

at least one redistribution structure interposed between the second chip and the third chip, the at least one redistribution structure having a redistribution line through which the second chip and the third chip are connected.

2. The package as claimed in claim 1, further comprising:

a molding portion surrounding the third chip; and

at least one through mold via (TMV) contact vertically passing through an entire thickness of the molding portion and connected to at least one of the second chip and the third chip through the at least one redistribution structure.

3. The package as claimed in claim 1, wherein the second chip to receive a power voltage or a ground voltage via the first chip and the at least one redistribution structure.

4. The package as claimed in claim 1, wherein the first chip includes a first through silicon via (TSV) contact, and

wherein the second chip includes:

a substrate;

an interconnection structure on the substrate; and

a second TSV contact passing through the substrate and the interconnection structure, the second TSV contact being aligned with and connected to the first TSV contact.

5. The package as claimed in claim 1, wherein the second chip includes a substrate, an interconnection structure on the substrate, and a TSV contact passing through the substrate, the TSV contact having a first end connected to an interconnection layer in the interconnection structure and a second end connected to the third chip through the at least one redistribution structure.

6. The package as claimed in claim 1, wherein the at least one redistribution structure includes:

a first redistribution structure on a surface of the second chip facing the third chip, the first redistribution structure including a plurality of first redistribution lines connected to an interconnection structure in the second chip; and

a second redistribution structure on a surface of the third chip facing the second chip, and connected to the third chip, the second redistribution structure being connected to the first redistribution structure through contact terminals.

7. The package as claimed in claim 1, wherein the at least one redistribution structure includes:

a conductive line connected to an internal circuit of at least one of the second chip or the third chip; and

at least one heater portion to provide heat to a portion of the first chip.

8. The package as claimed in claim 1, further comprising:

a molding portion surrounding the third chip; and

at least one TMV contact vertically passing through the molding portion and connected to at least one of the second chip and the third chip through the at least one redistribution structure,

wherein the at least one redistribution structure includes redistribution lines extending between the second chip and the third chip and between the molding portion and the second chip, the redistribution lines being connected to an interconnection structure within the third chip, portions of the redistribution lines extending to contact a top surface of the third chip and a top surface of the at least one TMV contact.

9. A package, comprising:

an image sensor chip having an interconnection structure to which signals are provided;

a logic chip vertically overlapping the image sensor chip, the logic chip to process a pixel signal output by the image sensor chip, the logic chip configured to generate a signal information by processing at least one of signals received from the image sensor chip; and

a memory chip vertically overlapping the image sensor chip and the logic chip, the logic chip being interposed between the image sensor chip and the memory chip, the memory chip configured to store the signal information received from the logic chip,

wherein the image sensor chip and the logic chip are connected via a conductive pad, and

wherein the logic chip and the memory chip are connected via at least one redistribution structure having a plurality of redistribution lines.

10. The package as claimed in claim 9, wherein no TSV contact is connected between the logic chip and the memory chip.

11. The package as claimed in claim 9, further comprising:

a molding portion surrounding the memory chip; and

at least one TMV contact vertically passing through an entire thickness of the molding portion and connected to at least one of the logic chip and the memory chip through the at least one redistribution structure.

12. The package as claimed in claim 9, further comprising:

a molding portion surrounding the memory chip;

a TMV contact vertically passing through the molding portion; and

a TSV contact vertically passing through the logic chip, the TSV contact being vertically aligned with the TMV contact.

13. The package as claimed in claim 9, further comprising:

a molding portion surrounding the memory chip;

a TMV contact vertically passing through the molding portion; and

a first TSV contact vertically passing through the image sensor chip, the first TSV contact being vertically aligned with the TMV contact.

14. The package as claimed in claim 13, further comprising a second TSV contact passing through the logic chip,

wherein the TMV contact, the first TSV contact, and the second TSV contact are vertically aligned with one another.

15. The package as claimed in claim 9, wherein the at least one redistribution structure includes:

a first redistribution structure on a surface of the logic chip facing the memory chip, the first redistribution structure including a plurality of first redistribution lines connected to an interconnection structure in the logic chip; and

a second redistribution structure on a surface of the memory chip facing the logic chip, and connected to the memory chip, the second redistribution structure being connected to the first redistribution structure through contact terminals.

16. A package, comprising:

a memory chip structure mounted on a package substrate, the memory chip structure including a memory chip, a molding portion surrounding the memory chip, and at least one TMV contact vertically passing through the molding portion;

an image sensor chip including a pixel array, an interconnection structure, and at least one first TSV contact; and

a logic chip interposed between the memory chip structure and the image sensor chip, the logic chip including at least one second TSV contact,

wherein the at least one TMV contact is vertically aligned with the at least one second TSV contact.

17. The package as claimed in claim 16, wherein the at least one TMV contact, the at least one first TSV contact, and the at least one second TSV contact are vertically aligned with one another.

18. The package as claimed in claim 16, further comprising:

at least one redistribution structure interposed between the memory chip structure and logic chip, wherein the logic chip is to receive one or more signals via the image sensor chip and the at least one redistribution structure.

19. The package as claimed in claim 16, wherein:

the memory chip structure includes a memory redistribution structure extending between the memory chip and the logic chip and between the molding portion and the logic chip, the memory redistribution structure connected to an interconnection structure within the memory chip, and

the memory redistribution structure includes an insulating layer covering the memory chip and the molding portion, and a plurality of memory redistribution lines on the insulating layer, portions of the plurality of memory redistribution lines extending through the insulating layer to contact a top surface of the memory chip and a top surface of the at least one TMV contact.

20. The package as claimed in claim 16, wherein no TSV contact is connected between the logic chip and the memory chip.