HIGH PERFORMANCE IMAGE SENSOR

• US 20200135792A1
• Filed: 03/13/2019
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Tung-Ting, Sze, Jhy-Jyi, Huang, Yimin
• Granted Patent: US 10,991,746 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/14607 Geometry of the photosensitive area
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 31/036 characterised by their crystalline structure or particular orientation of the crystalline planes

Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensing element disposed within a pixel region of a substrate. A plurality of conductive interconnect layers are disposed within a dielectric structure arranged along a first side of the substrate. A second side of the substrate includes a plurality of interior surfaces arranged directly over the image sensing element. The plurality of interior surfaces respectively include a substantially flat surface that extends along a plane.

Claims

1. An integrated chip, comprising:

an image sensing element disposed within a pixel region of a substrate;

a plurality of conductive interconnect layers disposed within a dielectric structure arranged along a first side of the substrate; and

wherein a second side of the substrate comprises a plurality of interior surfaces arranged directly over the image sensing element, the plurality of interior surfaces respectively comprising a substantially flat surface that extends along a plane.

2. The integrated chip of claim 1, wherein the plurality of interior surfaces comprise a group of substantially flat surfaces that extend along planes that intersect at a point that is between the plurality of interior surfaces.

3. The integrated chip of claim 2, wherein the point is arranged over the substrate and separated from the substrate by a non-zero distance.

4. The integrated chip of claim 1, wherein the plurality of interior surfaces respectively comprise a triangular shape.

5. The integrated chip of claim 1, further comprising:

an isolation region disposed between the pixel region and an adjacent pixel region, the isolation region defined by an upper surface of the substrate that extends in an unbroken loop surrounding the pixel region.

6. The integrated chip of claim 5, wherein the upper surface of the substrate is arranged along a horizontal plane that is vertically separated from tops of the plurality of interior surfaces by one or more non-zero distances.

7. The integrated chip of claim 5, wherein the plurality of interior surfaces define a first pyramidal shaped cavity separated from a second pyramidal shaped cavity by a ridge, the ridge vertically below the upper surface of the substrate.

8. The integrated chip of claim 5, wherein the upper surface is defined by jagged edges of the substrate as viewed from a top-view.

9. The integrated chip of claim 1, wherein the plurality of interior surfaces define a first pyramidal shaped cavity separated from a second pyramidal shaped cavity by a ridge, the ridge extending along a line between outer edges of the pixel region.

10. The integrated chip of claim 1, wherein the plurality of interior surfaces define a first pyramidal shaped protrusion separated from a second pyramidal shaped protrusion by a channel extending along a line between outer edges of the pixel region.

11. An integrated chip, comprising:

an image sensing element disposed within a substrate;

a plurality of conductive interconnect layers disposed within a dielectric structure arranged along a first side of the substrate; and

wherein a second side of the substrate comprises a plurality of interior surfaces arranged directly over the image sensing element and defining a plurality of topographical features, the plurality of interior surfaces comprising triangular shaped surfaces.

12. The integrated chip of claim 11, wherein the plurality of topographical features have a pyramidal shape with a substantially square shaped base.

13. The integrated chip of claim 11, wherein the substrate comprises silicon and the triangular shaped surfaces respectively extend along a (111) crystal plane of the silicon.

14. The integrated chip of claim 11, wherein a group of four of the plurality of interior surfaces extend along four planes that intersect at a point that is at or over a top of the group of four of the plurality of interior surfaces.

15. The integrated chip of claim 11, wherein the plurality of topographical features respectively comprise a pyramidal shaped protrusion.

16. The integrated chip of claim 11, wherein the plurality of topographical features respectively comprise a pyramidal shaped cavity.

17. The integrated chip of claim 11, further comprising:

an isolation region comprising a deep trench isolation structure including one or more dielectric materials arranged within a trench in a substantially planar upper surface of the substrate, wherein the deep trench isolation structure continuously extends around a pixel region comprising the image sensing element.

18. The integrated chip of claim 11,

wherein the plurality of topographical features are arranged in rows and columns within a pixel region comprising the image sensing element;

and

wherein a first row has a first number of topographical features and a second row has a second number of topographical features that is different than the first number of topographical features.

19. A method of forming an integrated chip, comprising:

forming an image sensing element within a substrate;

forming a masking layer on a first side of the substrate;

performing a first wet etching process on the first side of the substrate with the masking layer in place;

removing the masking layer; and

performing a second wet etching process on the first side of the substrate, wherein the first wet etching process and the second wet etching process collectively form a plurality of topographical features respectively defined by a plurality of substantially flat interior surfaces that extend along planes that intersect at a point.

20. The method of claim 19, further comprising:

forming one or more dielectric materials on the first side of the substrate and laterally between adjacent ones of the plurality of topographical features.