VIA SUPPORT STRUCTURE UNDER PAD AREAS FOR BSI BONDABILITY IMPROVEMENT

• US 20200135794A1
• Filed: 01/02/2020
• Published: 04/30/2020
• Est. Priority Date: 12/29/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Sin-Yao, Wang, Ching-Chun, Yaung, Dun-Nian, Hung, Feng-Chi
• Granted Patent: US 11,069,736 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire disposed within a dielectric structure on a substrate. A bond pad has a lower surface contacting the first interconnect wire. A via layer is vertically between the first interconnect wire and a second interconnect wire within the dielectric structure. The via layer includes a plurality of support vias having a first size and a plurality of additional vias having a second size that is smaller than the first size. The plurality of support vias extend from directly under the lower surface of the bond pad to laterally past outermost edges of the lower surface of the bond pad.

Claims

1. An integrated chip, comprising:

a first interconnect wire disposed within a dielectric structure on a substrate;

a bond pad having a lower surface contacting the first interconnect wire;

a via layer vertically between the first interconnect wire and a second interconnect wire within the dielectric structure; and

wherein the via layer comprises;

a plurality of support vias having a first size; and

a plurality of additional vias having a second size that is smaller than the first size, the plurality of support vias extending from directly under the lower surface of the bond pad to laterally past outermost edges of the lower surface of the bond pad.

2. The integrated chip of claim 1, wherein the lower surface of the bond pad laterally and continuously extends past two or more of the plurality of support vias.

3. The integrated chip of claim 1, wherein the bond pad further comprises a second lower surface contacting the first interconnect wire.

4. The integrated chip of claim 3, wherein the lower surface is separated from the second lower surface by a non-zero distance extending over one or more of the plurality of support vias.

5. The integrated chip of claim 3,

wherein the bond pad comprises a first protrusion and a second protrusion that extend outward from a horizontally extending surface of the bond pad, the first protrusion defined by the lower surface and the second protrusion defined by the second lower surface;

and

wherein the first protrusion is separated from the second protrusion by a dielectric material that directly overlies two or more of the plurality of support vias.

6. The integrated chip of claim 1, wherein the first size is greater than or equal to approximately 1.3 times the second size.

7. The integrated chip of claim 1, wherein the first interconnect wire is disposed between the second interconnect wire and the bond pad.

8. The integrated chip of claim 7, wherein the second interconnect wire contacts lower surfaces of the plurality of support vias and a third interconnect wire contacts lower surfaces of the plurality of additional vias, the second interconnect wire laterally separated from the third interconnect wire by the dielectric structure.

9. The integrated chip of claim 7, further comprising:

a second dielectric structure disposed on a second substrate that is bonded to the substrate, wherein the dielectric structure and the second dielectric structure are directly between the substrate and the second substrate.

10. An integrated chip, comprising:

a first interconnect wire disposed within a dielectric structure on a substrate;

a bond pad disposed on the first interconnect wire;

a first via layer vertically between the first interconnect wire and a second interconnect wire within the dielectric structure, wherein the first via layer comprises a first plurality of support vias having a first size and a first plurality of additional vias having a second size that is smaller than the first size; and

a second via layer comprising a second plurality of support vias contacting the second interconnect wire and a second plurality of additional vias, wherein the second plurality of support vias have a third size that is larger than a fourth size of the second plurality of additional vias.

11. The integrated chip of claim 10, wherein one or more of the first plurality of support vias are directly over one or more of the second plurality of support vias.

12. The integrated chip of claim 10,

wherein the bond pad comprises a first protrusion and a second protrusion extending outward from a horizontally extending surface of the bond pad;

and

wherein the first protrusion and the second protrusion are directly over the first plurality of support vias.

13. The integrated chip of claim 10, wherein the first size is greater than or equal to approximately 1.75 times the second size.

14. The integrated chip of claim 10, wherein the first interconnect wire comprises a slotted metal structure having one or more openings.

15. The integrated chip of claim 10, further comprising:

a second dielectric structure disposed on a second substrate that is bonded to the substrate, wherein the dielectric structure and the second dielectric structure are directly between the substrate and the second substrate.

16. An integrated chip, comprising:

a first interconnect wire arranged within a dielectric structure on a semiconductor substrate;

a bond pad contacting the first interconnect wire; and

a first via layer arranged within the dielectric structure between the first interconnect wire and a second interconnect wire, wherein the first via layer comprises a first plurality of vias that are spaced apart from one another by a substantially equal distance along a first direction and along a second direction perpendicular to the first direction.

17. The integrated chip of claim 16, wherein the semiconductor substrate comprises sidewalls defining an opening extending through the semiconductor substrate to the first interconnect wire.

18. The integrated chip of claim 17, wherein the bond pad is arranged directly between the sidewalls of the semiconductor substrate.

19. The integrated chip of claim 17, further comprising:

a dielectric material lining the sidewalls of the semiconductor substrate and extending over the first interconnect wire; and

wherein the bond pad has a horizontally extending surface resting on the dielectric material and one or more protrusions extending outward from the horizontally extending surface and through the dielectric material to contact the first interconnect wire.

20. The integrated chip of claim 16, wherein the first via layer further comprises one or more additional vias, which are laterally separated from the first plurality of vias and that are smaller than the first plurality of vias.