STACKED-DIE IMAGE SENSORS WITH SHIELDING

• US 20200135795A1
• Filed: 12/30/2019
• Published: 04/30/2020
• Est. Priority Date: 01/29/2016
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: MADURAWE, Raminda, MAURITZSON, Richard
• Granted Patent: US 11,133,346 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 25/043 Stacked arrangements of devices
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

Claims

1. Pixel circuitry for an image pixel, the pixel circuitry comprising:

a first integrated circuit die; and

a second integrated circuit die mounted to the first integrated circuit die, wherein the image pixel includes a photosensitive element in the first integrated circuit die and includes a floating diffusion region coupled to a gate terminal of a transistor, the transistor being in the first integrated circuit die, and wherein the image pixel includes a pixel output line in the second integrated circuit die.

2. The pixel circuitry defined in claim 1, wherein the image pixel includes an additional transistor that couples the transistor to the pixel output line, the additional transistor being in the second integrated circuit die.

3. The pixel circuitry defined in claim 2, wherein the additional transistor has a gate terminal configured to receive a row select control signal asserted during a pixel readout operation for the image pixel.

4. The pixel circuitry defined in claim 2, wherein a coupling structure at an interface of the first and second integrated circuit dies electrically connects the transistor to the additional transistor.

5. The pixel circuitry defined in claim 4, wherein the image pixel includes a charge transfer transistor interposed between the photosensitive element and the floating diffusion region, the charge transfer transistor being in the first integrated circuit die.

6. The pixel circuitry defined in claim 5, wherein the image pixel includes a reset transistor that couples a voltage supply line to the floating diffusion region, the reset transistor and the voltage supply line being in the first integrated circuit die.

7. The pixel circuitry defined in claim 4, wherein a shielding structure at the interface of the first and second integrated circuit dies surround the coupling structure.

8. The pixel circuitry defined in claim 1, wherein first integrated circuit die includes a first semiconductor layer and the second integrated circuit die includes a second semiconductor layer.

9. The pixel circuitry defined in claim 1, wherein the transistor has an additional terminal, and wherein a coupling structure at an interface of the first and second integrated circuit dies electrically connects the additional terminal of the transistor to the pixel output line.

10. An imaging system comprising:

an array of image pixels, each image pixel having a first portion in a first die and a second portion in a second die that is mounted to the first die, wherein;

the first portion of each image pixel includes a source follower transistor, and

the second portion of each image pixel includes a pixel output line that is coupled to the source follower transistor.

11. The imaging system defined in claim 10, wherein respective coupling structures in the first and second dies electrically connect the first portion of each image pixel to the second portion of each image pixel.

12. The imaging system defined in claim 11, wherein respective coupling structures include a first conductive structure in the first die and a second conductive structure in the second die, the second conductive structure being bonded to the first conductive structure.

13. The imaging system defined in claim 12, wherein the source follower transistor in a given image pixel of the array of image pixels is connected to the first conductive structure and the pixel output line in the given image pixel is connected to the second conductive structure.

14. The imaging system defined in claim 13, wherein the source follower transistor in an additional image pixel of the array of image pixels is connected to the first conductive structure.

15. The imaging system defined in claim 11, wherein each coupling structure in the respective coupling structures is surrounded by horizontal and vertical shielding structures.

16. The imaging system defined in claim 10, wherein the second portion of each image pixel includes a row select transistor that is interposed between the source follower transistor and the pixel output line.

17. The imaging system defined in claim 16, wherein the first portion of each image pixel includes a photosensitive element, a floating diffusion region coupled to the photosensitive region, a transistor interposed between the photosensitive element and the floating diffusion region, and a transistor coupling the floating diffusion region to a power supply line.

18. The imaging system defined in claim 10, further comprising:

analog and digital image sensor circuitry in a third die mounted to one of the first and second dies, the analog and digital image sensor circuitry being coupled to the pixel output line.

20. The array of image pixels defined in claim 18, wherein the floating diffusion region of each image pixel is entirely in the first integrated circuit die.

19. An array of image pixels, each image pixel comprising:

a photosensitive element in a first integrated circuit die;

a floating diffusion region in the first integrated circuit die;

a first transistor that couples the photosensitive element to the floating diffusion region;

a second transistor that couples the floating diffusion region to a voltage supply line, the voltage supply line being in the first integrated circuit die;

a row select transistor in a second integrated circuit die, the second integrated circuit die stacked on the first integrated circuit die; and

a pixel output line coupled to the row select transistor, the pixel outline line being in the second integrated circuit die.