DIGITAL X-RAY DETECTOR AND THIN-FILM TRANSISTOR ARRAY SUBSTRATE FOR THE SAME

• US 20200135796A1
• Filed: 10/28/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Jungjune, Yi, Youngjin, Han, Younghun, Chang, Youngyoung
• Granted Patent: US 11,348,963 B2
• Time in Patent Office: Days
• CPC Class Codes: G01T 1/20183 Arrangements for preventing or correcting crosstalk, e.g. optical or electrical arrangements for correcting crosstalk
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00

Abstract

The present disclosure relates to a digital X-ray detector and a thin-film transistor array substrate for the same. Disclosed is a thin-film transistor array substrate for a digital X-ray detector in which deterioration of electrical characteristics of a thin-film transistors made of an oxide semiconductor may be reduced or minimized and aging of a PIN diode caused by external moisture may be reduced or minimized. Further, disclosed is a digital X-ray detector including the array substrate. To this end, the array substrate includes a second protective layer having a variety of patterns so as to cover at least a portion of the PIN diode but not to cover the thin-film transistor. The second protective layer includes SiN_x. Thus, a de-hydrogenation path from the thin-film transistor may be secured and an external moisture barrier effect for the PIN diode may be achieved.

Claims

1. A thin-film transistor array substrate for a digital X-ray detector, comprising:

a base substrate;

a thin-film transistor disposed on the base substrate, wherein the thin-film transistor includes an active layer, a gate electrode, and a first electrode and a second electrode connected to the active layer;

a first protective layer disposed on the thin-film transistor;

a PIN diode disposed on the first protective layer, wherein the PIN diode includes a lower electrode connected to the thin-film transistor, a PIN layer on the lower electrode, and an upper electrode on the PIN layer;

a second protective layer covering at least a portion of the PIN diode, wherein the thin-film transistor is not covered with the second protective layer;

a bias electrode disposed on the PIN diode and connected to the upper electrode; and

a third protective layer disposed on the bias electrode, wherein the third protective layer covers the thin-film transistor and the PIN diode.

2. The thin-film transistor array substrate of claim 1, wherein the third protective layer is in direct contact with at least one of the first protective layer or the second protective layer.

3. The thin-film transistor array substrate of claim 1, wherein the third protective layer is in direct contact with both the first protective layer and the second protective layer.

4. The thin-film transistor array substrate of claim 1, wherein the thin-film transistor array substrate further comprises a planarization layer disposed between the second protective layer and the third protective layer,

wherein the planarization layer is in direct contact with at least one of the first protective layer or the second protective layer.

5. The thin-film transistor array substrate of claim 1, wherein the second protective layer covers a top surface and side surfaces of the PIN diode.

6. The thin-film transistor array substrate of claim 1, wherein the second protective layer covers an edge region of the PIN diode.

7. The thin-film transistor array substrate of claim 1, wherein the second protective layer is on the base substrate except for a region of the base substrate at which the thin-film transistor is disposed.

8. The thin-film transistor array substrate of claim 1, wherein the second protective layer further covers the gate electrode of the thin-film transistor.

9. The thin-film transistor array substrate of claim 1, wherein the second protective layer further covers one of a first contact hole or a second contact hole of the thin-film transistor.

10. The thin-film transistor array substrate of claim 1, wherein the second protective layer includes SiN_x.

11. The thin-film transistor array substrate of claim 1, wherein the thin-film transistor array substrate further comprises an inter-layer insulating layer disposed between the active layer and, the first electrode and the second electrode,

wherein the active layer is connected to the first electrode and the second electrode via a first contact hole and a second contact hole formed in the inter-layer insulating layer, respectively.

12. The thin-film transistor array substrate of claim 10, wherein each of the first protective layer, the inter-layer insulating layer and the third protective layer includes at least one of SiO₂ or SiON.

13. The thin-film transistor array substrate of claim 10, wherein the first protective layer includes SiN_x, wherein at least one of the first contact hole or the second contact hole is not covered with SiN_x.

14. A digital X-ray detector, comprising:

a thin-film transistor array substrate, the thin-film transistor array substrate including;

a base substrate;

a plurality of thin-film transistors on the base substrate, wherein each thin-film transistor include an active layer, a gate electrode, a first electrode, and a second electrode, the first and second electrodes connected to the active layer;

a first protective layer on the plurality of thin-film transistors;

a PIN diode on the first protective layer, wherein the PIN diode includes a lower electrode connected to the thin-film transistor, a PIN layer on the lower electrode, and an upper electrode on the PIN layer;

a second protective layer on a portion of the PIN diode, the second protective layer exposing a space of the PIN diode;

a bias electrode on the PIN diode and connected to the upper electrode; and

a third protective layer on the bias electrode, wherein the third protective layer extends over the thin-film transistor and the PIN diode; and

a scintillator layer disposed on the thin-film transistor array substrate.

15. The digital X-ray detector of claim 14, wherein the second protective layer is spaced apart from the thin-film transistor.

16. The digital X-ray detector of claim 14, wherein the bias electrode covers the space exposed by the second protective layer.

17. The digital X-ray detector of claim 14, further comprising a planarization layer between the third protective layer and the second protective layer.

18. The digital X-ray detector of claim 17, wherein the planarization layer is between the bias electrode and the second protective layer.