ATOMIC LAYER DEPOSITION AND PHYSICAL VAPOR DEPOSITION BILAYER FOR ADDITIVE PATTERNING

• US 20200135807A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Brew, Kevin W., Saraf, Iqbal Rashid, Ok, Injo, Saulnier, Nicole, Adusumilli, Praneet
• Granted Patent: US 11,158,788 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/52 Structure characterized by the electrode material, shape, etc.
• CPC Class Codes: G11C 2213/55 Structure including two electrodes, a memory active layer and at least two other layers which can be a passive or source or reservoir layer or a less doped memory active layer
• CPC Class Codes: H01L 21/0276 using an anti-reflective coating anti-reflective coating for lithography in general G03F7/09
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H10N 70/023 by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/8265 on sidewalls of dielectric structures, e.g. mesa or cup type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A method for manufacturing a semiconductor device includes forming a memory element in a dielectric layer. A first conductive layer is deposited on the dielectric layer and the memory element by atomic layer deposition, and a second conductive layer is deposited on the first conductive layer by physical vapor deposition. In the method, the first and second conductive layers are patterned into an electrode on the memory element.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a first dielectric layer;

forming a second dielectric layer on the first dielectric layer;

forming a third dielectric layer on the second dielectric layer;

forming a memory element in the second and third dielectric layers;

depositing by atomic layer deposition a first conductive layer on the third dielectric layer and the memory element;

depositing by physical vapor deposition a second conductive layer on the first conductive layer; and

patterning the first and second conductive layers into an electrode on the memory element;

wherein the second dielectric layer comprises silicon carbide; and

wherein the third dielectric layer comprises a different material from the second dielectric layer.

2. The method according to claim 1, wherein the patterning comprises performing a subtractive process which removes portions of the first and second conductive layers.

3. The method according to claim 1, wherein the first conductive layer comprises tantalum nitride (TaN).

4. The method according to claim 3, wherein a thickness of the first conductive layer is in a range about 3 nm to about 5 nm.

5. The method according to claim 4, wherein the second conductive layer comprises TaN.

6. The method according to claim 5, wherein a thickness of the second conductive layer is in a range about 20 nm to about 30 nm.

7. The method according to claim 1, wherein the memory element comprises at least one of a phase change material, an ovonic threshold switch and electrochemical metallization material.

8. The method according to claim 1, further comprising forming a bottom electrode in the first dielectric layer under the memory element and on an underlying contact, wherein a width of the bottom electrode is less than a width of the underlying contact.

9. The method according to claim 1, further comprising forming a mask structure on the second conductive layer.

10. The method according to claim 9, wherein forming the mask structure comprises:

forming a nitride layer on the second conductive layer;

forming an organic planarization layer on the nitride layer; and

forming a silicon anti-reflective coating layer on the organic planarization layer.

11. The method according to claim 10, further comprising:

forming a resist covering a first portion of the mask structure; and

removing a second portion of the mask structure not covered by the resist.

12. The method according to claim 9, further comprising patterning the mask structure so that the patterned mask structure covers a first region of the first and second conductive layers formed over the memory element, and exposes a second region of the first and second conductive layers.

13. The method according to claim 12, wherein the patterning of the first and second conductive layers into the electrode comprises removing the exposed second region of the first and second conductive layers.

14. The method according to claim 13, wherein the removing exposes portions of the third dielectric layer under the second region of the first and second conductive layers.

15. The method according to claim 1, wherein the second dielectric layer comprises nitrogen-doped silicon carbide.

16. A method for manufacturing a semiconductor device, comprising:

forming a first dielectric layer;

forming a second dielectric layer on the first dielectric layer;

forming a third dielectric layer on the second dielectric layer;

forming a phase change material in the second and third dielectric layers;

forming a bottom electrode in the first dielectric layer under the phase change material;

depositing by atomic layer deposition a conductive liner layer on the third dielectric layer and the phase change material;

depositing a conductive layer on the conductive liner layer; and

patterning the conductive liner layer and the conductive layer into a top electrode on the phase change material;

wherein the second dielectric layer comprises silicon carbide; and

wherein the third dielectric layer comprises a different material from the second dielectric layer.

17. The method according to claim 16, wherein the patterning comprises performing a subtractive process which removes portions of the conductive liner layer and the conductive layer.

18. The method according to claim 16, wherein the conductive layer is deposited on the conductive liner layer by physical vapor deposition.

19. A method for manufacturing a semiconductor device, comprising:

forming a contact in a first dielectric layer;

forming a bottom electrode on the contact;

forming a second dielectric layer on the first dielectric layer;

forming a third dielectric layer on the second dielectric layer, wherein the third dielectric layer comprises a low-k dielectric;

forming a memory element on the bottom electrode, wherein the memory element is surrounded by the second and third dielectric layers;

depositing by atomic layer deposition a first conductive layer on the third dielectric layer and the memory element;

depositing a second conductive layer on the first conductive layer; and

patterning the first and second conductive layers into a top electrode on the memory element;

wherein the second dielectric layer comprises silicon carbide; and

wherein the third dielectric layer comprises a different material from the second dielectric layer.

20. The method according to claim 19, wherein the patterning comprises performing a subtractive process which removes portions of the first and second conductive layers.