DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

• US 20200135824A1
• Filed: 08/08/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: BAEK, Jongjun, JEONG, Jaewoo, SO, Byungsoo
• Granted Patent: US 11,024,689 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H10K 50/12 comprising dopants
• CPC Class Codes: H10K 50/165 comprising dopants
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass
• CPC Class Codes: H10K 71/30 Doping active layers, e.g. electron transporting layers
• CPC Class Codes: H10K 71/40 Thermal treatment, e.g. annealing in the presence of a solvent vapour
• CPC Class Codes: Y02E 10/549 Organic PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A display apparatus includes a substrate, a first thin film transistor on the substrate, the first thin film transistor including an active layer including a source region, a drain region, and a channel region between the source region and the drain region, and a display device on the substrate and electrically connected to the first thin film transistor. The source region, the drain region, and the channel region include a first dopant and a second dopant, the second dopant being different from the first dopant. A concentration of the first dopant in the channel region is less than a concentration of the first dopant in the source region and the drain region.

Claims

1. A display apparatus, comprising:

a substrate;

a first thin film transistor on the substrate, the first thin film transistor including an active layer including a source region, a drain region, and a channel region between the source region and the drain region; and

a display device on the substrate and electrically connected to the first thin film transistor,

wherein the source region, the drain region, and the channel region include a first dopant and a second dopant, the second dopant being different from the first dopant, and

a concentration of the first dopant in the channel region is less than a concentration of the first dopant in the source region and the drain region.

2. The display apparatus as claimed in claim 1, wherein the first dopant is a p-type dopant.

3. The display apparatus as claimed in claim 1, wherein the second dopant is inert gas ions.

4. The display apparatus as claimed in claim 1, wherein a concentration of the second dopant is uniform in the source region, the drain region, and the channel region.

5. The display apparatus as claimed in claim 1, wherein:

the first thin film transistor further includes a gate electrode, a source electrode, and a drain electrode, the source electrode and the drain electrode respectively being connected to the source region and the drain region, and

the display device includes a first electrode electrically connected to one of the source electrode and the drain electrode, and a second electrode facing the first electrode.

6. The display apparatus as claimed in claim 5, wherein the display device further includes an intermediate layer between the first electrode and the second electrode, the intermediate layer including an emission layer.

7. The display apparatus as claimed in claim 1, wherein:

the active layer of the first thin film transistor includes polycrystalline silicon, and

the display apparatus further includes a second thin film transistor including an oxide semiconductor.

8. The display apparatus as claimed in claim 1, wherein the substrate is a flexible substrate.

9. A method of manufacturing a display apparatus, the method comprising:

forming a thin film transistor on a substrate, the thin film transistor comprising an active layer including a source region, a drain region, and a channel region between the source region and the drain region; and

forming a display device electrically connected to the thin film transistor,

wherein forming the thin film transistor includes;

forming an amorphous silicon layer on the substrate;

doping the amorphous silicon layer with a first dopant and a second dopant, the second dopant being different from the first dopant;

crystallizing the amorphous silicon layer; and

forming the active layer by patterning the silicon layer that is crystallized.

10. The method as claimed in claim 9, wherein forming the thin film transistor further includes:

forming a gate electrode on the active layer;

forming the source region, the drain region, and the channel region on the active layer by doping the active layer with the first dopant by using the gate electrode as a mask; and

forming a source electrode and a drain electrode that are respectively connected to the source region and the drain region,

wherein forming the display device includes forming a first electrode that is electrically connected to one of the source electrode and the drain electrode; and

forming a second electrode facing the first electrode.

11. The method as claimed in claim 10, wherein forming the display device further includes forming an intermediate layer between the first electrode and the second electrode, the intermediate layer including an emission layer.

12. The method as claimed in claim 9, wherein the first dopant and the second dopant are dispersed in the amorphous silicon layer simultaneously with crystallizing the amorphous silicon layer.

13. The method as claimed in claim 9, wherein crystallizing the amorphous silicon layer is at a temperature of about 350°

C. to about 450°

C.

14. The method as claimed in claim 9, wherein the first dopant is a p-type dopant.

15. The method as claimed in claim 9, wherein the second dopant is inert gas ions.

16. The method as claimed in claim 9, wherein doping the second dopant is performed after doping the first dopant.

17. The method as claimed in claim 16, wherein a mass of the second dopant is greater than a mass of the first dopant.

18. The method as claimed in claim 9, wherein the amorphous silicon layer is completely doped with the first dopant and the second dopant before crystallizing the amorphous silicon layer.