DISPLAY APPARATUS AND ELECTRONIC DEVICE

• US 20200135826A1
• Filed: 10/24/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Tsuboi, Hiromasa
• Granted Patent: US 10,998,392 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

A display apparatus including pixels is provided. Each pixels comprises a light-emitting element, a first transistor having a drain region connected to an anode of the light-emitting element, and a second transistor having a drain region connected to a gate electrode of the first transistor. The drain region of the first transistor includes a first region and a second region arranged between the first region and a channel region and having a higher resistivity than the first region. The drain region of the second transistor includes a third region and a fourth region arranged between the third region and a channel region and having a higher resistivity than the third region. A length of the second region in a direction in which a current flows is longer than that of the fourth region in a direction in which a current flows.

Claims

1. A display apparatus including a plurality of pixels arranged in an array on a substrate,

each of the plurality of pixels comprising a light-emitting element, a first transistor having a drain region connected to an anode of the light-emitting element, and a second transistor having a drain region connected to a gate electrode of the first transistor,

wherein the drain region of the first transistor includes a first region and a second region arranged between the first region and a channel region of the first transistor and having a higher resistivity than the first region,

the drain region of the second transistor which is connected to the gate electrode of the first transistor includes a third region and a fourth region arranged between the third region and a channel region of the second transistor and having a higher resistivity than the third region, and

in an orthogonal projection with respect to the substrate, a length of the second region in a direction in which a current flows is longer than a length of the fourth region in a direction in which a current flows.

2. The apparatus according to claim 1, wherein the first region and the second region are formed from semiconductor materials having the same conductivity type,

an impurity concentration of the second region is lower than an impurity concentration of the first region,

the third region and the fourth region are formed from semiconductor materials having the same conductivity type, and

an impurity concentration of the fourth region is lower than an impurity concentration of the third region.

3. The apparatus according to claim 1, wherein the first region and the third region each are formed from a compound of a semiconductor and a metal, and

the second region and the fourth region are formed from semiconductor materials.

4. The apparatus according to claim 3, wherein the drain region of the first transistor further includes a fifth region arranged between the second region and the channel region of the first transistor and having a higher resistivity than the second region.

5. The apparatus according to claim 3, wherein the drain region of the second transistor further includes a sixth region arranged between the fourth region and the channel region of the second transistor and having a higher resistivity than the fourth region.

10. The apparatus according to claim 1, wherein a source region of the first transistor includes a seventh region and an eighth region arranged between the seventh region and the channel region of the first transistor and having a higher resistivity than the seventh region, and

in an orthogonal projection with respect to the substrate, a length of the second region in a direction in which a current flows is longer than a length of the eighth region in a direction in which a current flows.

11. The apparatus according to claim 1, wherein each of the plurality of pixels further comprises a third transistor configured to short-circuit two terminals of the light-emitting element.

12. The apparatus according to claim 11, wherein a source region of the third transistor includes a ninth region and a 10th region arranged between the ninth region and the channel region of the third transistor and having a higher resistivity than the ninth region, and

in an orthogonal projection with respect to the substrate, a length of the 10th region in a direction in which a current flows is longer than a length of the fourth region in a direction in which a current flows.

13. The apparatus according to claim 12, wherein a drain region of the third transistor includes an 11th region and a 12th region arranged between the 11th region and the channel region of the third transistor and having a higher resistivity than the 11th region, and

in an orthogonal projection with respect to the substrate, a length of the 12th region in a direction in which a current flows is shorter than a length of the fourth region in a direction in which a current flows.

14. The apparatus according to claim 1, wherein each of the plurality of pixels further comprises a fourth transistor having a drain region connected to a source region of the first transistor and configured to control emission or non-emission of the light-emitting element, and

the fourth transistor operates in a linear region in an emission period in which the light-emitting element is caused to emit light.

15. The apparatus according to claim 14, wherein the drain region of the fourth transistor includes a 13th region and a 14th region arranged between the 13th region and a channel region of the fourth transistor and having a higher resistivity than the 13th region, and

in an orthogonal projection with respect to the substrate, a length of the second region in a direction in which a current flows is longer than a length of the 14th region in a direction in which a current flows.

16. The apparatus according to claim 12, wherein each of the plurality of pixels further comprises a fourth transistor having a drain region connected to the source region of the first transistor and configured to control emission or non-emission of the light-emitting element,

the fourth transistor operates in a linear region in an emission period in which the light-emitting element is caused to emit light,

the drain region of the fourth transistor includes a 13th region and a 14th region arranged between the 13th region and a channel region of the fourth transistor and having a higher resistivity than the 13th region, and

in an orthogonal projection with respect to the substrate, a length of the 10th region in a direction in which a current flows is longer than a length of the 14th region in a direction in which a current flows.

17. The apparatus according to claim 16, wherein in an orthogonal projection with respect to the substrate, a length of the second region in a direction in which a current flows is longer than a length of the 14th region in a direction in which a current flows.

18. The apparatus according to claim 15, wherein the source region of the fourth transistor includes a 15th region and a 16th region arranged between the 15th region and the channel region of the fourth transistor and having a higher resistivity than the 15th region, and

in an orthogonal projection with respect to the substrate, a length of the 16th region in a direction in which a current flows is shorter than a length of the fourth region in a direction in which a current flows.

19. The apparatus according to claim 1, wherein a source region of the second transistor includes a 17th region and an 18th region arranged between the 17th region and the channel region of the second transistor and having a higher resistivity than the 17th region, and

in an orthogonal projection with respect to the substrate, a length of the 18th region in a direction in which a current flows is longer than a length of the fourth region in a direction in which a current flows.

20. An electronic device comprising:

a display apparatus according to claim 1; and

a control unit configured to control driving of the display apparatus.

6. A display apparatus including a plurality of pixels arranged in an array on a substrate,

each of the plurality of pixels comprising a light-emitting element, a first transistor having a drain region connected to an anode of the light-emitting element, and a second transistor having a drain region connected to a gate electrode of the first transistor,

wherein the drain region of the first transistor includes a first region and a second region arranged between the first region and a channel region of the first transistor,

the drain region of the second transistor which is connected to the gate electrode of the first transistor includes a third region and a fourth region arranged between the third region and a channel region of the second transistor,

the second region has the same conductivity type as the conductivity type of the first region and a lower impurity concentration than the first region,

the fourth region has the same conductivity type as the conductivity type of the third region and a lower impurity concentration than the third region, and

in an orthogonal projection with respect to the substrate, a length of the second region in a direction in which a current flows is longer than a length of the fourth region in a direction in which a current flows.

7. The apparatus according to claim 6, wherein the drain region of the first transistor further includes a first compound region formed from a compound of a semiconductor and a metal,

the first region is arranged between the first compound region and the second region,

the drain region of the second transistor further includes a second compound region formed from a compound of a semiconductor and a metal, and

the third region is arranged between the second compound region and the fourth region.

8. A display apparatus including a plurality of pixels arranged in an array on a substrate,

each of the plurality of pixels comprising a light-emitting element, a first transistor having a drain region connected to an anode of the light-emitting element, and a second transistor having a drain region connected to a gate electrode of the first transistor,

wherein the drain region of the first transistor includes a first region and a second region arranged between the first region and a channel region of the first transistor,

the drain region of the second transistor which is connected to the gate electrode of the first transistor includes a third region and a fourth region arranged between the third region and a channel region of the second transistor,

the first region and the third region each are formed from a compound of a semiconductor and a metal,

the second region and the fourth region are formed from semiconductor materials, and

in an orthogonal projection with respect to the substrate, a length of the second region in a direction in which a current flows is longer than a length of the fourth region in a direction in which a current flows.

9. The apparatus according to claim 8, wherein the drain region of the first transistor further includes a fifth region arranged between the second region and the channel region of the first transistor,

the fifth region has the same conductivity type as a conductivity type of the second region and has a lower impurity concentration than the second region,

the drain region of the second transistor further includes a sixth region arranged between the fourth region and the channel region of the second transistor, and

the sixth region has the same conductivity type as a conductivity type of the fourth region and has a lower impurity concentration than the fourth region.