SUBSTRATE COMPRISING RECESSED INTERCONNECTS AND A SURFACE MOUNTED PASSIVE COMPONENT

• US 20200135839A1
• Filed: 10/31/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: KANG, Kuiwon, KIM, Chin-Kwan, WE, Hong Bok, YEON, Jaehyun
• Granted Patent: US 11,075,260 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19106 in a mirrored arrangement on two different side of a common die mounting substrate

Abstract

A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect.

Claims

1. A device comprising:

a substrate including;

a dielectric layer; and

a plurality of interconnects formed in the dielectric layer; and

a discrete passive component coupled to the substrate through a solder interconnect, wherein the solder interconnect is located within the dielectric layer.

2. The device of claim 1, wherein the solder interconnect is located in a cavity of the dielectric layer.

3. The device of claim 1, wherein the substrate includes a cavity that is filled with a via and the solder interconnect.

4. The device of claim 3, wherein the via includes a curved surface coupled to the solder interconnect.

5. The device of claim 3, wherein the cavity has a height that is in a range of 15-80 micrometers (μ

m).

6. The device of claim 1, wherein the discrete passive component is located over a first surface of the substrate that faces away from a die.

7. The device of claim 1, wherein the discrete passive component and a die are located over a second surface of the substrate.

8. The device of claim 1, wherein the discrete passive component includes a multi-layer ceramic capacitor (MLCC).

9. The device of claim 1, wherein the discrete passive component includes a maximum thickness of 110 micrometers (μ

m).

10. The device of claim 1, wherein the substrate includes a core layer.

11. The device of claim 1, wherein the dielectric layer includes a plurality of dielectric layers.

12. The device of claim 1, wherein the substrate includes a plurality of solder interconnects having a pitch of 0.35 millimeters (mm) or less.

13. The device of claim 1, wherein the device is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.

25. The method of claim 1, wherein coupling the discrete capacitor to the substrate include coupling the discrete capacitor to a first surface of the substrate that faces away from a die.

14. A device comprising:

a substrate including;

a dielectric layer; and

a plurality of interconnects formed in the dielectric layer;

means for capacitance coupled to the substrate through means for soldering, wherein the means for soldering is located within the dielectric layer; and

a die coupled to the substrate.

15. The device of claim 14, wherein the means for soldering includes:

means for first soldering located in a first cavity of the dielectric layer; and

means for second soldering located in a second cavity of the dielectric layer.

16. The device of claim 14, wherein the substrate includes:

a first cavity that is filled with a first via and means for first soldering; and

a second cavity that is filled with a second via and means for second soldering.

17. The device of claim 16, wherein the first via includes a curved surface coupled to the means for first soldering, and the second via includes a curved surface coupled to the means for second soldering.

18. The device of claim 14, wherein the means for capacitance is located over a first surface of the substrate and the die is located over a second surface of the substrate.

19. The device of claim 14, wherein the means for capacitance and the die are located over a second surface of the substrate.

20. The device of claim 14, wherein the substrate includes a core layer.

21. A method for fabricating a device, comprising:

providing a substrate that includes;

a dielectric layer;

a cavity in the dielectric layer; and

a plurality of interconnects formed in the dielectric layer; and

coupling a discrete capacitor to the substrate through a solder interconnect such that the solder interconnect is located within the cavity of the dielectric layer.

22. The method of claim 21, wherein the cavity is filled with a via and the solder interconnect.

23. The method of claim 22, wherein the via includes a curved surface coupled to the solder interconnect.

24. The method of claim 21, wherein the cavity has a height that is in a range of 15-80 micrometers (μ

m).

26. The method of claim 21, wherein coupling the discrete capacitor to the substrate include coupling the discrete capacitor to a second surface of the substrate that is coupled to a die.

27. The method of claim 21, wherein the substrate includes a core layer.

28. The method of claim 21, wherein the substrate includes a plurality of dielectric layers.