METHOD AND DEVICE FOR PATTERNING THICK LAYERS

• US 20200135841A1
• Filed: 10/31/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: West, Jeffrey Alan, Williams, Byron Lovell, Robbins, John Britton
• Granted Patent: US 10,811,492 B2
• Time in Patent Office: Days
• CPC Class Codes: G03F 1/42 Alignment or registration features, e.g. alignment marks on the mask substrates
• CPC Class Codes: G03F 7/16 Coating processes; Apparatus therefor applying coatings to base materials in general B05; applying photosensitive compositions to base for photographic purposes G03C1/74
• CPC Class Codes: G03F 7/20 Exposure; Apparatus therefor photographic printing apparatus for making copies G03B27/00
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 28/60 Electrodes

Abstract

A method of fabricating an integrated circuit includes applying photoresist to a MESA dielectric layer of a semiconductor structure, to generate a photoresist layer. The method also includes exposing the photoresist layer with a grayscale mask, to generate an exposed photoresist layer. The photoresist exposed layer includes a thick photoresist pattern in a first region, a thin photoresist pattern in a second region where a height of the thin photoresist pattern is less than half a height of the thick photoresist pattern, and a gap region between the thick photoresist pattern and the thin photoresist pattern.

Claims

1. A method of fabricating an integrated circuit, the method comprising:

applying photoresist to a MESA dielectric layer of a semiconductor structure, to generate a photoresist layer; and

exposing the photoresist layer with a grayscale mask, to generate an exposed photoresist layer, the exposed photoresist layer comprising;

a thick photoresist pattern in a first region;

a thin photoresist pattern in a second region wherein a height of the thin photoresist pattern is less than half a height of the thick photoresist pattern; and

a gap region between the thick photoresist pattern and the thin photoresist pattern.

2. The method of claim 1, wherein exposing the photoresist layer with the grayscale mask, to generate the exposed photoresist layer further comprises generating a high voltage capacitance region, wherein a height of the high voltage capacitance region is greater than the height of the thick photoresist pattern.

3. The method of claim 2, further comprising:

determining whether the thin photoresist pattern is aligned to metal features below the MESA dielectric layer; and

etching the MESA dielectric layer, in response to determining that the thin photoresist pattern is aligned to the metal features, to generate an alignment mark in a scribe lane; and

removing the thin photoresist pattern and the thick photoresist pattern, in response to determining that the thin photoresist pattern is not aligned to the metal features.

4. The method of claim 3, further comprising:

forming a MESA capacitor dielectric in the high voltage capacitance region, in response to determining that the thin photoresist pattern is aligned to the metal features.

5. The method of claim 4, wherein the alignment mark comprises a MESA graybox, wherein a height of the MESA graybox is less than half of a height of the MESA capacitor dielectric.

6. The method of claim 3, wherein the alignment mark comprises:

an outer MESA graybox; and

an inner MESA graybox within the outer MESA graybox, wherein a height of the inner MESA graybox is less than a height of the outer MESA graybox.

7. The method of claim 1, wherein the thin photoresist pattern comprises:

an outer photoresist box; and

an inner photoresist box inside the outer photoresist box, wherein a height of the inner photoresist box is less than a height of the outer photoresist box.

8. The method of claim 7, wherein the outer photoresist box is beneath a medium density dithered pattern of the grayscale mask and the inner photoresist box is beneath a lower density dithered pattern of the grayscale mask.

9. The method of claim 7, further comprising, before applying photoresist to the MESA dielectric layer:

forming an inter-layer dielectric (ILD) oxide layer on a substrate;

forming a metal frame structure in the ILD oxide layer;

forming a metal plate structure in the ILD oxide layer; and

forming the MESA dielectric layer over the ILD oxide layer; and

wherein the metal frame structure is below the outer photoresist box and the metal plate structure is below the inner photoresist box.

10. The method of claim 9, wherein the metal frame structure and the metal plate structure comprise copper, aluminum, or an aluminum alloy.

11. The method of claim 1, wherein the thick photoresist pattern is beneath an opaque region of the grayscale mask, the thin photoresist pattern is beneath a dithered region of the grayscale mask, and the gap region is beneath a transparent region of the grayscale mask.

12. The method of claim 1, wherein the height of the thin photoresist pattern is less than a third of the height of the thick photoresist pattern.

13. A semiconductor structure, comprising:

a semiconductor substrate; and

a MESA dielectric layer overlying the semiconductor substrate, the MESA dielectric layer comprising;

a MESA capacitor dielectric in a capacitor region of the semiconductor structure, the MESA capacitor dielectric having a first height;

a MESA graybox in a scribe lane of the semiconductor structure, the MESA graybox having a second height, wherein the second height of the MESA graybox is less than half of the first height of the MESA capacitor dielectric; and

a thin dielectric layer between the MESA capacitor dielectric and the MESA graybox, the thin dielectric layer having a third height, wherein the third height of the thin dielectric layer is less than the second height of the MESA graybox.

14. The semiconductor structure of claim 13, wherein the MESA graybox is an outer MESA graybox, the semiconductor structure further comprising:

an inner MESA graybox within the outer MESA graybox, wherein the inner MESA graybox has a fourth height, and wherein the fourth height of the inner MESA graybox is less than the second height of the outer MESA graybox and greater than the third height of the thin dielectric layer.

15. The semiconductor structure of claim 14, further comprising:

an inter-layer dielectric layer (ILD) oxide layer under the MESA dielectric layer;

a metal frame structure below the outer MESA graybox in the ILD oxide layer; and

a metal plate structure under the inner MESA graybox in the ILD oxide layer.

16. The semiconductor structure of claim 13, further comprising:

an ILD oxide layer under the MESA dielectric layer; and

a metal structure in the ILD oxide layer, the metal structure below the MESA graybox.

17. The semiconductor structure of claim 13, wherein the second height of the MESA graybox is more than a quarter the first height of the MESA capacitor dielectric.

18. A method of fabricating an integrated circuit, the method comprising:

imaging a MESA alignment mark on a structure, wherein the MESA alignment mark comprises a MESA graybox of a MESA dielectric layer, and wherein a height of the MESA graybox is less than half of a height of a MESA capacitor dielectric of the MESA dielectric layer;

imaging a metal layer, while imaging the MESA alignment mark, wherein the metal layer is beneath the MESA alignment mark; and

determining whether the MESA alignment mark is aligned with the metal layer, based on imaging the MESA alignment mark and imaging the metal layer.

19. The method of claim 18, further comprising scrapping the structure in response to determining that the MESA alignment mark is not aligned with the metal layer.

20. The method of claim 18, further comprising performing additional processing on the structure, forming the integrated circuit, in response to determining that the MESA alignment mark is aligned with the metal layer.