INTEGRATED CHIP AND METHOD OF FORMING THEREOF

• US 20200135851A1
• Filed: 12/12/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Meng-Han, Tsair, Yong-Shiuan
• Granted Patent: US 11,239,313 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

An integrated chip comprises a substrate, an isolation structure and a gate structure. The isolation structure comprises one or more dielectric materials within the substrate and has sidewalls defining an active region in the substrate. The active region has a channel region, a source region, and a drain region separated from the source region by the channel region along a first direction. The source, drain and channel regions respectively have first, second and third widths along a second direction perpendicular to the first direction. The third width is larger than the first and second widths. The gate structure comprises a first gate electrode region having a first composition of one or more materials and a second gate electrode region having a second composition of one or more materials different than the first composition of one or more materials.

Claims

1. An integrated chip, comprising:

a substrate;

an isolation structure comprising one or more dielectric materials within the substrate and having sidewalls defining an active region in the substrate, wherein the active region has a channel region, a source region, and a drain region separated from the source region by the channel region along a first direction, the source region has a first width along a second direction perpendicular to the first direction, the drain region has a second width along the second direction, and the channel region has a third width along the second direction and larger than the first width and the second width; and

a gate structure extending over the channel region, the gate structure comprising a first gate electrode region having a first composition of one or more materials and a second gate electrode region having a second composition of one or more materials different than the first composition of one or more materials.

2. The integrated chip of claim 1, wherein the isolation structure has surfaces defining one or more divots recessed below an uppermost surface of the isolation structure.

3. The integrated chip of claim 2, wherein the second gate electrode region is over the one or more divots.

4. The integrated chip of claim 3, wherein the first gate electrode region is over the one or more divots.

5. The integrated chip of claim 2, wherein the second gate electrode region is separated from the one or more divots by the first gate electrode region along the second direction.

6. The integrated chip of claim 1, wherein the second gate electrode region extends past opposing sides of the channel region along the first direction.

7. The integrated chip of claim 1, wherein a length of the first gate electrode region along the first direction is greater than a length of the channel region along the first direction.

8. The integrated chip of claim 7, wherein a length of the second gate electrode region along the first direction is less than the length of the first gate electrode region along the first direction.

9. The integrated chip of claim 7, wherein a length of the second gate electrode region along the first direction is greater than the length of the channel region along the first direction.

10. The integrated chip of claim 1, wherein the active region changes between the first width and the third width at a position that is directly below the second gate electrode region.

11. The integrated chip of claim 1, wherein the first composition of one or more materials comprises an n-type gate metal, and the second composition of one or more materials comprises a p-type gate metal.

12. The integrated chip of claim 1, wherein the first composition of one or more materials has a work function different from a work function of the second composition of one or more materials.

13. The integrated chip of claim 1, wherein the first gate electrode region laterally abuts the second gate electrode region along the first direction and along the second direction.

14-20. -20. (canceled)

21. An integrated chip, comprising:

an isolation structure arranged within a substrate and defining an active region in the substrate;

a first doped region disposed within the active region;

a second doped region disposed within the active region and separated from the first doped region by a middle region of the active region along a first direction, wherein the first doped region has a first width along a second direction perpendicular to the first direction, the second doped region has a second width along the second direction, and the middle region has a third width along the second direction and greater than the first width or the second width; and

a gate structure extending over the active region along the second direction, the gate structure comprising a first gate electrode region having a first work function and a plurality of second gate electrode regions having second work functions different from the first work function, the plurality of second gate electrode regions are separated by a center portion of the first gate electrode region.

22. The integrated chip of claim 21, wherein the second gate electrode regions are arranged along the second direction.

23. The integrated chip of claim 21, wherein the first gate electrode region comprises a peripheral portion surrounding the second gate electrode regions.

24. The integrated chip of claim 21, wherein the first gate electrode region comprises an n-type gate metal, and the plurality of second gate electrode regions comprises a p-type gate metal.

25. An integrated chip, comprising:

a source region and a drain region disposed in a substrate;

a channel region arranged between the source region and the drain region along a first direction and extending past the source region and the drain region along a second direction perpendicular to the first direction, wherein the source region, the drain region, and the channel region are semiconductor bodies having boundaries limited and defined by an isolation structure; and

a gate structure overlying and covering a top surface of the channel region;

wherein the source region has a first width along the second direction, the drain region has a second width along the second direction, and the channel region has a third width along the second direction and greater than the first width or the second width.

26. The integrated chip of claim 25, wherein the gate structure comprises a first gate electrode region having a first composition of one or more materials and a second gate electrode region having a second composition of one or more materials different than the first composition of one or more materials.

27. The integrated chip of claim 25, wherein the third width is about 2% to about 10% greater than the first width or the second width.