NANOSHEET FET BOTTOM ISOLATION

• US 20200135853A1
• Filed: 11/19/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: BAO, RUQIANG, BI, ZHENXING, Cheng, Kangguo, XU, ZHENG
• Granted Patent: US 11,024,711 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A technique relates to a semiconductor device. A rare earth material is formed on a substrate. An isolation layer is formed at an interface of the rare earth material and the substrate. Channel layers are formed over the isolation layer. Source or drain (S/D) regions are formed on the isolation layer.

Claims

1. A semiconductor device comprising:

a rare earth material formed on a substrate;

an isolation layer formed at an interface of the rare earth material and the substrate;

channel layers formed over the isolation layer; and

source or drain (S/D) regions formed on the isolation layer.

2. The semiconductor device of claim 1, wherein a dielectric layer is on the channel layers.

3. The semiconductor device of claim 1, wherein one or more work function materials are formed on the channel layers and on the isolation layer.

4. The semiconductor device of claim 3, wherein the isolation layer separates the one or more work function materials from the substrate.

5. The semiconductor device of claim 1, wherein the isolation layer physically separates and electrically isolates the S/D regions from the substrate.

6. The semiconductor device of claim 1, wherein the rare earth material comprises a rare earth oxide.

7. The semiconductor device of claim 1, wherein the rare earth material comprises a rare earth oxide with a cubic lattice.

8. The semiconductor device of claim 1, wherein the rare earth material comprises a rare earth oxide having a lattice constant that comprises about twice a lattice constant of a material of the substrate.

9. The semiconductor device of claim 1, wherein a lattice structure of the rare earth material substantially matches a lattice structure of the channel layers.

10. The semiconductor device of claim 1, wherein the isolation layer comprises an oxide material.

11. The semiconductor device of claim 1, wherein the isolation layer is formed as an oxide of a material of the substrate.

12. The semiconductor device of claim 1, wherein the isolation layer comprises silicon.

13. The semiconductor device of claim 1, wherein the isolation layer comprises silicon dioxide.

14. The semiconductor device of claim 1, wherein the isolation layer comprises oxygen molecules.

15. The semiconductor device of claim 1, wherein a dielectric layer is on the channel layers and the dielectric layer is comprises a dielectric constant greater than 3.9.

16. The semiconductor device of claim 15, wherein the dielectric layer comprises hafnium.

17. The semiconductor device of claim 15, wherein the dielectric layer comprises aluminum.

18. The semiconductor device of claim 15, wherein the dielectric layer comprises tantalum.

19. The semiconductor device of claim 15, wherein the dielectric layer comprises zirconium.

20. The semiconductor device of claim 1, wherein the S/D regions formed on the rare earth material.