Strained Nanowire CMOS Device and Method of Forming

• US 20200135854A1
• Filed: 12/20/2019
• Published: 04/30/2020
• Est. Priority Date: 10/07/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Cheng-Yi, Chiang, Hung-Li, Yang, Yu-Lin, Yeh, Chih Chieh, Yeo, Yee-Chia, Liu, Chi-Wen
• Granted Patent: US 10,727,298 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a first fin and a second fin, each of the first fin and the second fin comprising alternating first semiconductor material layers and second semiconductor material layers;

forming a dummy gate structure over the first fin and the second fin;

forming a first dielectric layer over the first fin and the second fin;

removing a first portion the dummy gate structure to form a first recess, the first recess exposing a first channel region of the first fin;

removing at least a portion of the second semiconductor material layers in the first channel region of the first fin;

forming a second dielectric layer over the first channel region of the first fin;

removing a second portion of the dummy gate structure to form a second recess, the second recess exposing a second channel region of the second fin;

removing at least a portion of the first semiconductor material layers in the second channel region of the second fin; and

forming a gate electrode over the first channel region and the second channel region.

2. The method of claim 1 further comprising removing an uppermost second semiconductor material layer in the first channel region prior to forming the gate electrode.

3. The method of claim 2, wherein removing a first portion the dummy gate structure to form a first recess, the first recess exposing a first channel region of the first fin and removing the uppermost second semiconductor material layer in the first channel region comprises:

recessing the first portion of the dummy gate structure to expose the uppermost second semiconductor material layer in the first channel region;

etching the uppermost second semiconductor material layer in the first channel region; and

removing a remaining portion of the first portion of the dummy gate structure.

4. The method of claim 1, wherein removing at least a portion of the second semiconductor material layers recesses a sidewall of the second semiconductor material layers more than the first semiconductor material layers in the first channel region.

5. The method of claim 1, wherein removing at least a portion of the first semiconductor material layers recesses a sidewall of the first semiconductor material layers more than the second semiconductor material layers in the second channel region.

6. The method of claim 1, wherein the first channel region has a first conductivity type and the second channel region has a second conductivity type.

7. The method of claim 1, wherein removing at least the portion of the first semiconductor material layers comprises completely removing the first semiconductor material layers in the second channel region, and further comprising, after completely removing the first semiconductor material layers in the second channel region, rounding the second semiconductor material layers in the second channel region.

8. The method of claim 7, wherein rounding comprises forming an oxidation layer over the second semiconductor material layers in the second channel region using a thermal oxidation process.

9. The method of claim 8, wherein rounding further comprises removing the oxidation layer.

10. The method of claim 9, wherein a width of the second semiconductor material layers prior to removing the first semiconductor material layers in the second channel region is in a range of 5 nm to 10 nm, and a width of the second semiconductor material layers after rounding is in a range of 1 nm to 7 nm.

11. A method of forming a semiconductor device, the method comprising:

forming a first fin and a second fin, each of the first fin and the second fin comprising an alternating epitaxial structure, the alternating epitaxial structure comprising alternating first semiconductor material layers and second semiconductor material layers, the alternating epitaxial structure of each of the first fin and the second fin comprising a bottommost first semiconductor material layer on a substrate;

forming a sacrificial gate structure over a first channel region of the first fin and a second channel region of the second fin;

forming a dielectric layer over the first fin and the second fin adjacent the sacrificial gate structure;

removing a first portion of the sacrificial gate structure to expose the first channel region;

indenting sidewalls of the first semiconductor material layers from sidewalls of the second semiconductor material layers in the first channel region of the first fin;

removing a second portion of the sacrificial gate structure to expose the second channel region;

indenting sidewalls of the second semiconductor material layers from sidewalls of the first semiconductor material layers in the second channel region of the second fin; and

forming a replacement gate over the first channel region and the second channel region.

12. The method of claim 11, wherein the substrate comprises a strain relaxed buffer layer over a semiconductor layer.

13. The method of claim 11 further comprising removing the bottommost first semiconductor material layer in the second channel region.

14. The method of claim 13, wherein at least a portion of remaining first semiconductor layers remain in the second channel region.

15. The method of claim 11 further comprising removing an uppermost second epitaxial layer from the first fin in the first channel region.

16. The method of claim 11, wherein the replacement gate extends between adjacent ones of the second semiconductor material layers in the first channel region, and wherein the replacement gate extends between adjacent ones of the first semiconductor material layers in the second channel region.

17. The method of claim 11 further comprising forming a sacrificial layer over one of the first channel region and the second channel region while indenting semiconductor layers in the other of the first channel region and the second channel region.

18. A method of forming a semiconductor device, the method comprising:

forming a first fin and a second fin, each of the first fin and the second fin comprising alternating first semiconductor material layers and second semiconductor material layers;

forming a dummy gate structure over a first channel region of the first fin and a second channel region of the second fin;

forming a dielectric layer over the first fin and the second fin adjacent the dummy gate structure;

at least partially recessing the first semiconductor material layers in the first channel region;

at least partially recessing the second semiconductor material layers in the second channel region; and

forming a replacement gate structure over the first channel region and the second channel region.

19. The method of claim 18, wherein at least partially recessing the first semiconductor material layers and at least partially recessing the second semiconductor material layers comprise:

removing a first portion of the dummy gate structure;

selectively etching sidewalls of the first semiconductor material layers in a first channel region of the first fin while the second channel region is protected;

removing a second portion of the dummy gate structure; and

selectively etching sidewalls of the second semiconductor material layers in the second channel region of the second fin while the first channel region is protected.

20. The method of claim 18, wherein the at least partially recessing the second semiconductor material layers comprises completely removing the second semiconductor material layers, and further comprising rounding the first semiconductor material layers in the second channel region.