Germanium Nitride Layers on Semiconductor Structures, and Methods for Forming the Same

• US 20200135855A1
• Filed: 12/20/2019
• Published: 04/30/2020
• Est. Priority Date: 08/15/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Holland, Martin Christopher, Vellianitis, Georgios
• Granted Patent: US 11,031,468 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02112 characterised by the material of the layer
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Provided herein are semiconductor structures that include germanium and have a germanium nitride layer on the surface, as well as methods of forming the same. The described structures include nanowires and fins. Methods of the disclosure include metal-organic chemical vapor deposition with a germanium precursor. The described methods also include using a N₂H₄ vapor.

Claims

1. A device comprising:

a semiconductor substrate;

a germanium nanowire on the semiconductor substrate, the germanium nanowire comprising a channel; and

a germanium nitride layer surrounding a circumference of the channel, the germanium nitride layer having a thickness that is more than a monolayer.

2. The device of claim 1, wherein the germanium nitride layer has a carbon concentration of no more than about 5×

10¹⁶ atoms/cm<sup>−

3</sup>.

3. The device of claim 1, wherein an interface between the germanium nanowire and the germanium nitride layer has an interface trap density (D_IT) of no more than about 5×

10¹¹ eV<sup>−

1</sup> cm<sup>−

2</sup>.

4. The device of claim 1, wherein a surface of the semiconductor substrate underlying the channel is spaced apart from a bottom surface of the channel.

5. The device of claim 1, wherein the germanium nitride layer is between the germanium nanowire and the semiconductor substrate.

6. The device of claim 1, wherein the semiconductor substrate abuts the germanium nitride layer.

7. The device of claim 1, further comprising a dielectric layer on the germanium nitride layer, the dielectric layer surrounding the circumference of the channel.

8. The device of claim 7, further comprising a gate electrode on the dielectric layer, the gate electrode surrounding the circumference of the channel.

9. A device comprising:

a substrate;

a fin structure on the substrate, the fin structure comprising germanium;

a channel region in the fin structure; and

a germanium nitride layer on the channel region, the germanium nitride layer having a thickness that is more than a monolayer.

10. The device of claim 9 further comprising a gate dielectric layer on the germanium nitride layer, such that the germanium nitride layer is between the gate dielectric layer and the fin structure.

11. The device of claim 10 further comprising isolation regions along opposing sides of the fin structure, wherein the germanium nitride layer extends over the isolation regions.

12. The device of claim 11, wherein the germanium nitride layer completely separates the gate dielectric layer from the isolation regions.

13. The device of claim 9, wherein the substrate has a surface, the fin structure having a width and a height that is greater than the width, the fin structure extending away from the surface of the substrate to the height.

14. The device of claim 9, wherein the thickness of the germanium nitride layer is at least about 1 nanometer.

15. A device comprising:

a first nanostructure and a second nanostructure over a substrate, the first nanostructure and the second nanostructure comprising a germanium-containing material;

a first germanium nitride layer over the first nanostructure and a second germanium nitride layer over the second nanostructure, the first germanium nitride layer and the second germanium nitride layer having a thickness that is more than a monolayer;

a first dielectric layer over the first germanium nitride layer and a second dielectric layer over the second germanium nitride layer;

a source region and a drain region, the first nanostructure and the second nanostructure being interposed between the source region and the drain region; and

a gate electrode over the first dielectric layer and the second dielectric layer.

16. The device of claim 15, wherein the first germanium nitride layer is separated from the second germanium nitride layer.

17. The device of claim 15, wherein a carbon concentration of the first germanium nitride layer is no more than about 5×

10¹⁶ atoms/cm<sup>−

3</sup>.

18. The device of claim 15, wherein an interface trap density (DIT) of an interface between the first nanostructure and the first germanium nitride layer is less than about 5×

1011 eV<sup>−

1</sup> cm<sup>−

2</sup>.

19. The device of claim 15, wherein the first germanium nitride layer is free of oxygen.

20. The device of claim 15, wherein a region between the first nanostructure and the substrate is free of other germanium-containing nanostructures, and wherein the gate electrode extends between the first nanostructure and the substrate.