Source/Drain Metal Contact and Formation Thereof

• US 20200135858A1
• Filed: 08/30/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiu, Shih-Chuan, Chang, Chia-Hao, You, Jia-Chuan, Lin, Tien-Lu, Lin, Yu-Ming, Wang, Chih-Hao
• Granted Patent: US 11,043,558 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present disclosure provides a method for semiconductor fabrication. The method includes epitaxially growing source/drain feature on a fin; forming a silicide layer over the epitaxial source/drain feature; forming a seed metal layer on the silicide layer; forming a contact metal layer over the seed metal layer using a bottom-up growth approach; and depositing a fill metal layer over the contact metal layer.

Claims

1. A method for semiconductor fabrication, comprising:

epitaxially growing source/drain feature on a fin;

forming a silicide layer over the epitaxial source/drain feature;

forming a seed metal layer on the silicide layer;

forming a contact metal layer over the seed metal layer using a bottom-up growth approach; and

depositing a fill metal layer over the contact metal layer.

2. The method of claim 1, wherein the seed metal layer is formed to be in direct contact with the silicide layer.

3. The method of claim 1, wherein sidewalls of the seed metal layer are in direct contact with a dielectric material layer.

4. The method of claim 3, wherein the seed metal layer is selectively formed such that the seed metal layer grows on the silicide layer but not on any dielectric surfaces.

5. The method of claim 1, wherein the silicide layer has a thickness of about 5 nm to about 7 nm, and wherein the seed metal layer has a thickness of about 1 nm to about 5 nm.

6. The method of claim 1, wherein the silicide layer is formed between first and second dummy gate stacks that are disposed on the fin, wherein the method further comprises, after the formation of the silicide layer and before the formation of the contact metal layer, performing a gate replacement process to replace the first and second dummy gate stacks with first and second metal gate stacks.

7. The method of claim 1, further comprising, before the formation of the silicide layer, performing a gate replacement process to replace first and second dummy gate stacks with first and second metal gate stacks, the first and second metal gate stacks defining an opening in which the silicide layer is formed.

8. The method of claim 1, wherein the bottom-up growth approach for the formation of the contact metal layer is selective such that the contact metal layer is formed only on a conductive surface and not any dielectric surfaces, and wherein the bottom-up growth approach for the formation of the contact metal layer includes a chemical vapor deposition (CVD) process conducted using a precursor, wherein a flow rate of the precursor is equal to or less than about 100 standard cubic centimeter per minute (sccm), and a gas pressure of the precursor is equal to or less than about 50 Torr.

9. The method of claim 1, wherein a precursor to form the contact metal layer includes tungsten hexafluoride (WF₆) or tungsten chloride (WCl₅), and the contact metal layer includes tungsten, and wherein a precursor used to form the seed metal layer includes Co(tBuDAD)₂ and the seed metal layer includes cobalt.

10. The method of claim 1, further comprising implanting atoms into spacers that are disposed adjacent the contact metal layer to laterally expand a volume of the spacers, thereby increasing adhesion between the contact metal layer and the spacers, wherein the atoms implanted into the spacers are larger than silicon atoms.

11. The method of claim 1, further comprising performing a chemical-mechanical planarization (CMP) process to remove the fill metal layer and a top portion of the contact metal layer.

12. A semiconductor device, comprising:

a fin disposed on a substrate;

first and second metal gate stacks disposed on the fin;

first and second spacers disposed on respective sidewalls of the first and second metal gate stacks;

a source/drain feature disposed on the fin and between the first and second metal gate stacks;

a silicide layer disposed over the source/drain feature;

a seed metal layer disposed on the silicide layer; and

a bottom-up metal layer disposed over the seed layer and between the first and second spacers, wherein the bottom-up metal layer is in direct contact with the first and second spacers.

13. The semiconductor device of claim 12, wherein the seed metal layer includes a first metal and the bottom-up metal layer includes a second metal different from the first metal in composition.

14. The semiconductor device of claim 13, wherein the bottom-up metal layer includes tungsten and the seed metal layer includes cobalt.

15. The semiconductor device of claim 13, wherein the bottom-up metal layer includes copper and the seed metal layer includes tungsten.

16. The semiconductor device of claim 12, wherein the bottom-up metal layer is in direct contact with the seed metal layer without any glue layers between the bottom-up metal layer and the seed metal layer.

17. The semiconductor device of claim 12, wherein a total thickness of the silicide layer and the bottom-up metal layer is at least three times of a width of the bottom-up metal layer, the width being in a direction along which the fin runs.

18. A semiconductor device, comprising:

a fin disposed on a substrate;

first and second metal gate stacks disposed on the fin;

first and second spacers disposed on respective sidewalls of the first and second metal gate stacks;

a source/drain feature disposed on the fin and between the first and second metal gate stacks; and

a contact feature landing on the source/drain feature, wherein the contact feature further includes

a silicide layer disposed over the source/drain feature;

a seed metal layer of a first metal disposed on the silicide layer; and

a bottom-up metal layer of a second metal disposed over the seed layer and between the first and second spacers, wherein the bottom-up metal layer is in direct contact with the first and second spacers, wherein the second metal is different from the first metal in composition.

19. The semiconductor device of claim 18, wherein the bottom-up metal layer includes tungsten and the seed metal layer includes cobalt.

20. The semiconductor device of claim 18, wherein

the fin is a first fin, wherein the semiconductor device includes a second fin;

the source/drain feature is a merged source/drain feature emerged from the first and second fins;

the silicide layer wraps around the merged source/drain feature;

the seed metal layer wraps around the silicide layer; and

the bottom-up metal layer landing on a concave surface of the merged source/drain feature.