MULTI-GATE DEVICE AND METHOD OF FABRICATION THEREOF

• US 20200135862A1
• Filed: 12/20/2019
• Published: 04/30/2020
• Est. Priority Date: 01/13/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHEN, I-Sheng, WU, Cheng-Hsien, YEH, Chih Chieh, YEO, Yee-Chia
• Granted Patent: US 11,043,561 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Claims

1. A method of forming a semiconductor device, the method comprising:

providing a fin having a channel region, wherein the fin includes first, second, and third layers;

removing at least a portion of the second layer from the channel region to form a gap between the first and third layers;

forming an interposing feature in the channel region at least partially wrapping around the first layer and the third layer;

forming a metal layer along opposing sidewalls of the interposing feature for performing a scavenging process to the interposing feature,

wherein a distance between the first layer and third layer is determined based on a predetermined scavenging threshold of the scavenging process.

2. The method of claim 1, wherein the forming the interposing feature includes:

forming a first material in the channel region to form a first interfacial layer portion at least partially wrapping around the first layer and a second interfacial layer portion at least partially wrapping around the third layer.

3. The method of claim 1, where the first material includes an oxide-containing material.

4. The method of claim 1, wherein at least one of the first layer and the third layer has a profile determined based on the predetermined scavenging threshold.

5. The method of claim 1, each of the first and third layers has a rounded profile.

6. The method of claim 1, where the scavenging process is performed to tune at least one of a flat band voltage and a threshold voltage of the semiconductor device.

7. The method of claim 1, wherein the scavenging process is performed to reduce the equivalent oxide thickness (EOT) of the semiconductor device.

8. A method, comprising:

forming a fin element including first, second, and third semiconductor layers;

removing at least a portion of the second semiconductor layer from a channel region of the fin element to form a gap between the first and third semiconductor layers;

forming an interposing feature in the channel region, wherein the interposing feature includes;

a dielectric layer at least partially wrapping around the first semiconductor layer and the third semiconductor layer;

depositing a metal layer at least partially wrapping around the interposing feature for performing a scavenging process to the interposing feature.

9. The method of claim 8, wherein the metal layer includes a first material, and

wherein the gap is free of the first material.

10. The method of claim 8, wherein the interposing feature includes:

a first interfacial layer portion at least partially wrapping around the first semiconductor layer; and

a second interfacial layer portion at least partially wrapping around the third semiconductor layer,

wherein the dielectric layer at least partially wrapping around the first interfacial layer portion and the second interfacial layer portion.

11. The method of claim 10, further comprising:

performing an annealing process to the metal layer to cause the scavenging process to the first interfacial layer portion and second interfacial layer portion.

12. The method of claim 11, wherein all areas of the first and second interfacial layer portions are scavenged during the scavenging process.

13. The method of claim 8, wherein a distance between the first layer and third layer is determined based on a predetermined scavenging threshold of the scavenging process.

14. The method of claim 8, wherein at least one of the first layer and the third layer has a profile determined based on a predetermined scavenging threshold of the scavenging process.

15. A method, comprising:

providing a substrate including a fin element, the fin element including a bottom layer disposed over the substrate, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer;

forming a dummy gate structure in a channel region of the fin element;

forming a source/drain feature in a source/drain region of the fin element adjacent to the dummy gate structure;

removing the dummy gate structure to form an opening in the channel region to expose the fin element in the channel region;

removing at least a portion of the middle layer of the fin element exposed in the opening;

forming an interposing feature in the channel region, wherein the interposing feature at least partially wrapping around the bottom layer and the top layer;

forming a metal layer along opposing sidewalls of the interposing feature in the channel region; and

causing a scavenging process to the interposing feature by performing an annealing process to the metal layer.

16. The method of claim 15, further comprising:

after the removing of the at least a portion of the middle layer, etching the bottom and top layers in the channel region that each of the bottom and top layers has a predetermined profile.

17. The method of claim 16, further comprising:

after the etching of the bottom and top layers, growing a silicon layer on the bottom and top layers.

18. The method of claim 16, wherein the predetermined profile is determined based on a predetermined scavenging threshold of the scavenging process.

19. The method of claim 15, wherein a distance between the bottom layer and the top layer is determined based on a predetermined scavenging threshold of the scavenging process.

20. The method of claim 15, wherein the bottom layer includes silicon germanium or germanium.