MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application

• US 20200135863A1
• Filed: 12/13/2019
• Published: 04/30/2020
• Est. Priority Date: 04/29/2015
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Han, Jin-Woo, Widjaja, Yuniarto, Or-Bach, Zvi, Maheshwari, Dinesh
• Granted Patent: US 11,201,215 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 : and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1083 : with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 : characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/32 : the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/40114 : the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 : the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42344 : with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42356 : Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78645 : with multiple gate
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H03K 19/0948 : using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/20 : characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 19/21 : EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors

Abstract

A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

Claims

1-43. -43. (canceled)

44. A semiconductor device configured to function as a semiconductor memory device or a transistor with increased on-state drain current, said semiconductor device comprising:

a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type;

a buried layer having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type;

a body having said first conductivity type;

a source region and a drain region each having said second conductivity type and being separated by said body;

a gate positioned in between said source region and said drain region; and

a select gate spaced apart from said gate.

45. The semiconductor device of claim 44, wherein said select gate is positioned in between said drain region and said gate, and an insulating gap region is formed between said select gate and said gate.

46. The semiconductor device of claim 44, wherein said gate is floating and stores non-volatile data in the absence of power.

47. The semiconductor device of claim 46, wherein applying a voltage to said buried layer region enhances current flow to said gate.

54. The semiconductor device of claim 44 comprising a fin structure extending from said substrate.

48. A semiconductor device configured to function as a semiconductor memory device or a transistor with increased on-state drain current, said semiconductor device comprising:

a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type;

a buried layer having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type;

a body having said first conductivity type;

a source region and a drain region each having said second conductivity type and being separated by said body;

a gate positioned in between said source region and said drain region; and

a control gate spaced apart from said gate.

49. The semiconductor device of claim 48, wherein said control gate is positioned in between said drain region and said gate, and an insulating gap region is formed between said control gate and said gate.

50. The semiconductor device of claim 49, wherein said control gate overlaps said insulating gap region and at least partially overlaps said gate.

51. The semiconductor device of claim 48, wherein said gate is floating and stores non-volatile data in the absence of power.

52. The semiconductor device of claim 51, wherein applying a voltage to said buried layer region enhances current flow to said gate.

53. The semiconductor device of claim 48 comprising a fin structure extending from said substrate.