QUANTUM DOT DEVICES

• US 20200135864A1
• Filed: 06/24/2017
• Published: 04/30/2020
• Est. Priority Date: 06/24/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Singh, Kanwaljit, Clarke, James S., Veldhorst, Menno, Vandersypen, Lieven Mark Koenraad
• Granted Patent: US 11,322,591 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: G06N 10/00 Quantum computing, i.e. information processing based on quantum-mechanical phenomena
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/127 Quantum box structures
• CPC Class Codes: H01L 29/15 Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices such structures applied for the control of light G02F1/017, applied in semiconductor lasers H01S5/34
• CPC Class Codes: H01L 29/423 not carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/437 Superconductor materials
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66977 Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
• CPC Class Codes: H01L 29/7613 Single electron transistors; Coulomb blockade devices H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
• CPC Class Codes: H01L 29/7786 : with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

Claims

1. A quantum dot device, comprising:

a quantum well stack;

a plurality of first gate lines above the quantum well stack; and

a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines;

wherein the first gate lines or the second gate lines include a magnetic material.

2. The quantum dot device of claim 1, wherein the magnetic material includes cobalt or nickel.

3. The quantum dot device of claim 1, wherein the first gate lines are at least partially between the second gate lines and the quantum well stack.

4. The quantum dot device of claim 1, wherein the first gate lines have a pitch between 5 nanometers and 200 nanometers.

5. The quantum dot device of claim 4, wherein the second gate lines have a pitch between 5 nanometers and 200 nanometers.

6. The quantum dot device of claim 1, wherein the second gate lines include quantum dot gates extending toward the quantum well stack between one or more adjacent pairs of first gate lines.

7. The quantum dot device of claim 6, wherein an interior quantum dot gate has at least 8 nearest neighbor quantum dot gates.

8. The quantum dot device of claim 6, wherein an interior quantum dot gate has fewer than 8 nearest neighbor quantum dot gates.

9-15. -15. (canceled)

16. A quantum dot device, comprising:

a quantum well stack;

a plurality of first gate lines above the quantum well stack; and

a plurality of second gate lines above the quantum well stack;

wherein the second gate lines are perpendicular to the first gate lines, the second gate lines include quantum dot gates extending toward the quantum well stack between one or more adjacent pairs of first gate lines, and an interior quantum dot gate has fewer than 8 nearest neighbor quantum dot gates.

17. The quantum dot device of claim 16, wherein the interior quantum dot gate has 4 nearest neighbor quantum dot gates.

18. The quantum dot device of claim 16, wherein the interior quantum dot gate has 2 nearest neighbor quantum dot gates.

19. The quantum dot device of claim 16, wherein the first gate lines or the second gate lines include a magnetic material or a superconducting material.

20. A quantum computing device, comprising:

a quantum processing device, wherein the quantum processing device includes a quantum well stack, a plurality of first gate lines above the quantum well stack, a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines;

a non-quantum processing device, coupled to the quantum processing device, to control electrical signals applied to the first and second gate lines; and

a memory device to store data generated during operation of the quantum processing device;

wherein the first gate lines include a magnetic material, or the first gate lines include a superconducting material and the non-quantum processing device is to control current applied to the first gate lines to cause the first gate lines to generate a magnetic field gradient.

21. The quantum computing device of claim 20, further comprising:

a cooling apparatus to maintain a temperature of the quantum processing device below 10 Kelvin.

22. The quantum computing device of claim 20, wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

23. The quantum computing device of claim 20, wherein the second gate lines include quantum dot gates extending toward the quantum well stack between one or more adjacent pairs of first gate lines, and an interior quantum dot gate has fewer than 8 nearest neighbor quantum dot gates.

24. The quantum computing device of claim 20, wherein the quantum well stack includes a layer of silicon and a layer of silicon oxide between the layer of silicon and the first gate lines.

25. The quantum computing device of claim 20, wherein electron-based or hole-based quantum dots are formed in the quantum well stack during operation of the quantum processing device.