Semiconductor devices, radio frequency devices and methods for forming semiconductor devices

• US 20200135865A1
• Filed: 10/24/2018
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Radosavljevic, Marko, Then, Han Wui, Dasgupta, Sansaptak, Fischer, Paul B., Hafez, Walid M.
• Granted Patent: US 10,840,341 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0895 Tunnel injectors
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence

Abstract

A semiconductor device is proposed. The semiconductor device includes a group III-N semiconductor layer, an electrically insulating material layer located on the group III-N semiconductor layer, and a metal contact structure located on the electrically insulating material layer. An electrical resistance between the metal contact structure and the group III-N semiconductor layer through the electrically insulating material layer is smaller than 1*10⁻⁷Ω for an area of 1 mm². Further, semiconductor devices including a low resistance contact structure, radio frequency devices, and methods for forming semiconductor devices are proposed.

Claims

1. A semiconductor device comprising:

a group III-N semiconductor layer;

an electrically insulating material layer located on the group III-N semiconductor layer; and

a metal contact structure located on the electrically insulating material layer,

wherein an electrical resistance between the metal contact structure and the group III-N semiconductor layer through the electrically insulating material layer is smaller than 1*10<sup>−

7</sup>Ω

for an area of 1 mm².

2. The semiconductor device according to claim 1,

wherein a thickness of the electrically insulating material layer is at least 0.3 nm and at most 2 nm.

3. The semiconductor device according to claim 1,

wherein the electrically insulating material layer is an oxide layer.

4. The semiconductor device according to claim 1,

wherein a thickness of the group III-N semiconductor layer is at least 100 nm and at most 8 μ

m.

5. The semiconductor device according to claim 1,

comprising a highly doped group III-N contact portion located between the electrically insulating material layer and a portion of the group III-N semiconductor layer, wherein a doping concentration of the highly doped group III-N contact portion is at least 1*10¹⁹ cm⁻

3.

6. The semiconductor device according to claim 5,

wherein a vertical dimension of the highly doped group III-N contact portion is at least 20 nm and at most 250 nm.

7. The semiconductor device according to claim 1,

wherein the group III-N semiconductor layer is located on a group III-N buffer layer.

8. The semiconductor device according to claim 7,

wherein the group III-N buffer layer has a thickness of at least 100 nm and of at most 8 μ

m.

9. The semiconductor device according to claim 1,

wherein the metal contact structure comprises a sublayer comprising at least one of titanium, titanium nitride, and tantalum nitride.

10. The semiconductor device according to claim 9,

wherein the sublayer of the metal contact structure has a thickness of at least 1 nm and of at most 20 nm.

11. The semiconductor device according to claim 1,

wherein the metal contact structure comprises a metal portion comprising at least one of copper, tungsten and aluminum.

12. The semiconductor device according to claim 11,

wherein the metal portion of the metal contact structure is located on the sublayer of the metal contact structure.

13. The semiconductor device according to claim 1,

wherein the group III-N semiconductor layer is located on a silicon substrate.

14. The semiconductor device according to claim 1,

wherein the metal contact structure is a source contact of a field effect transistor of the semiconductor device.

15. The semiconductor device according to claim 1, further comprising a further metal contact structure.

16. The semiconductor device according to claim 15,

wherein the semiconductor device is configured to conduct a current between the metal contact structure and the further metal contact structure through the electrically insulating material layer and the group III-N semiconductor layer.

17. The semiconductor device according to claim 15,

wherein the further metal contact structure is a drain contact of the field effect transistor of the semiconductor device.

18. The semiconductor device according to claim 17,

wherein the field effect transistor of the semiconductor device further comprises a polarization layer located on the group III-N semiconductor layer and positioned laterally between the source contact and the drain contact of the field effect transistor.

19. The semiconductor device according to claim 1,

wherein the metal contact structure provides an electrical contact to at least one of an anode region of a diode, a cathode region of a diode, a drain region of a transistor, a source region of a transistor, a collector region of a transistor, an emitter region of a transistor, and a base region of a transistor of the semiconductor device.

20. A semiconductor device comprising:

a group III-N semiconductor layer; and

a low resistive contact structure comprising a highly doped group III-N contact portion, an electrically insulating material layer and a metal contact structure,

wherein the low resistive contact structure is located on the group III-N semiconductor layer,

wherein the electrically insulating material layer is located on the highly doped group III-N contact portion, and the metal contact structure is located on the electrically insulating material layer,

wherein the highly doped group III-N contact portion has a doping concentration of at least 1*10¹⁹ cm<sup>−

3</sup>.

21. The semiconductor device according to claim 20,

wherein a thickness of the electrically insulating material layer is at least 0.3 nm and at most 2 nm.

22. A radio frequency device comprising:

a field effect transistor; and

a low resistive contact structure of the field effect transistor, wherein the low resistive contact structure comprises a highly doped group III-N contact portion, an electrically insulating material layer and a metal contact structure,

wherein the metal contact structure provides a drain contact or a source contact of the field effect transistor,

wherein the field effect transistor is configured to switch between an on state and an off state with a frequency of at least 1 GHz.

23. The radio frequency device according to claim 22,

wherein a thickness of the electrically insulating material layer is at least 0.3 nm and at most 2 nm.

24. A method for forming a semiconductor device, the method comprising:

forming an electrically insulating material layer on a group III-N semiconductor layer; and

forming a metal contact structure on the electrically insulating material layer;

wherein an electrical resistance between the metal contact structure and the group III-N semiconductor layer through the electrically insulating material layer is smaller than 1*10<sup>−

7</sup>Ω

for an area of 1 mm².

25. The method according to claim 24,

wherein the electrically insulating material layer has a thickness of at least 0.3 nm and at most 2 nm.