METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES

• US 20200135868A1
• Filed: 10/15/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HAN, Hui-An, LIU, Ding-I, FAN, Yuh-Ta, HSU, Kai-Shiung
• Granted Patent: US 11,069,534 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/3115 Doping the insulating layers
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/3215 Doping the layers
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a gate dielectric layer over a channel region;

forming a first conductive layer over the gate dielectric layer;

forming a protective layer at a surface region of the first conductive layer;

forming a metallic layer by applying a metal containing gas on the protective layer;

removing the metallic layer by a wet etching operation using a solution,

wherein the protective layer is resistant to the solution of the wet etching operation.

2. The method of claim 1, wherein the first conductive layer is TaN.

3. The method of claim 2, wherein the protective layer is formed by introducing boron into the surface region of the first conductive layer.

4. The method of claim 3, wherein the protective layer is formed by applying a boron containing gas to a surface of the first conductive layer.

5. The method of claim 4, wherein the boron containing gas is B₂H₆.

6. The method of claim 3, wherein the protective layer is formed by implanting boron into the surface region of the first conductive layer.

7. The method of claim 2, wherein the metallic layer includes a W layer.

8. The method of claim 7, wherein the W layer is formed by a gas containing WF₆.

9. The method of claim 2, wherein the solution includes H₃PO₄.

10. The method of claim 2, wherein a loss of a thickness of the TaN layer after the wet etching operation is less than 0.5 nm compared with a thickness of the TaN layer as formed.

11. A method of manufacturing a semiconductor device, comprising:

forming a gate dielectric layer over a channel region;

forming a first conductive layer over the gate dielectric layer;

forming a second conductive layer over the first conductive layer;

forming a protective layer on a surface or at a surface region of the first conductive layer;

forming a metallic layer by using a metal containing gas over the protective layer; and

removing the metallic layer by a wet etching operation using a solution containing H₃PO₄,

wherein the protective layer is resistant to the solution of the wet etching operation.

12. The method of claim 11, wherein the first conductive layer is TiN and the second conductive layer is TaN.

13. The method of claim 11, wherein the protective layer is formed by applying a gas containing one element selected from the group consisting of B, N, C, and Si to a surface of the second conductive layer.

14. The method of claim 11, wherein the protective layer is formed by CVD or ALD.

15. The method of claim 11, wherein the metallic layer includes a W layer formed by using a gas containing WF₆.

16. The method of claim 11, further comprising, after the metallic layer is formed, performing an annealing operation at a temperature from 450°

C. to 650°

C.

17. The method of claim 11, further comprising, after forming the first conductive layer and before forming the second conductive layer:

forming a first cap layer over the first conductive layer;

performing an annealing operation after the first cap layer is formed; and

removing the first cap layer after the annealing operation.

18. The method of claim 17, wherein the first cap layer is made of crystalline, polycrystalline or amorphous silicon.

19. The method of claim 11, wherein:

the forming a metallic layer includes applying the metal containing gas over the protective layer to form a nucleation layer, and forming a TiN layer over the nucleation layer,

after the TiN layer is formed a second annealing operation is performed.

20. A semiconductor device, comprising:

a channel layer;

a gate dielectric layer disposed over the channel layer;

a first conductive layer disposed over the gate dielectric layer;

a protective layer disposed on the first conductive layer;

a second conductive layer disposed over the protective layer, wherein;

the protective layer includes one selected from the group consisting of a boron containing layer, a silicon containing layer, and a carbon containing layer.