INTEGRATED CIRCUIT LAYOUTS WITH SOURCE AND DRAIN CONTACTS OF DIFFERENT WIDTHS

• US 20200135869A1
• Filed: 09/24/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ciou, Shang-Syuan, Zhuang, Hui-Zhong, Yang, Jung-Chan, Tien, Li-Chun
• Granted Patent: US 11,302,787 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0843 Source or drain regions of field-effect devices
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor device includes an active region in a substrate. The active region extends in a first direction. The semiconductor device further includes a gate structure extending in a second direction different from the first direction. The gate structure extends across the active region. The semiconductor device further includes a plurality of source/drain contacts extending in the second direction and overlapping a plurality of source/drain regions in the active region on opposite sides of the gate structure. A first source/drain contact of the plurality of source/drain contacts has a first width, and a second source/drain contact of the plurality of source/drain contacts has a second width less than the first width.

Claims

1. A semiconductor device comprising:

an active region in a substrate, wherein the active region extends in a first direction;

a gate structure extending in a second direction different from the first direction, wherein the gate structure extends across the active region; and

a plurality of source/drain contacts extending in the second direction and overlapping a plurality of source/drain regions in the active region on opposite sides of the gate structure, wherein a first source/drain contact of the plurality of source/drain contacts has a first width, and a second source/drain contact of the plurality of source/drain contacts has a second width less than the first width.

2. The semiconductor device of claim 1, further comprising a conductive layer extending in the first direction, wherein the conductive layer is electrically coupled to the first source/drain contact and the second source/drain contact.

3. The semiconductor device of claim 2, further comprising a first via, wherein the first via electrically couples the conductive layer to the first source/drain contact.

4. The semiconductor device of claim 3, further comprising a second via, wherein the second via electrically couples the conductive layer to the second source/drain contact.

5. The semiconductor device of claim 4, wherein the first via has a dimension greater than a dimension of the second via.

6. The semiconductor device of claim 1, a spacing between the first source/drain contact and the gate structure is smaller than a spacing between the second source/drain contact and the gate structure.

7. A semiconductor device comprising:

a plurality of active regions in a substrate, wherein each of the plurality of active regions extends in a first direction and is separated from one another in a second direction different from the first direction;

a plurality of gate structures extending in the second direction, wherein each of the plurality of gate structures extends across each active region of the plurality of active regions;

a plurality of first source/drain contacts extending in the second direction and overlapping a plurality of first source/drain regions in a first active region of the plurality of active regions on opposite sides of the plurality of gate structures, wherein a first set of first source/drain contacts of the plurality of first source/drain contacts have a first width, and a second set of first source/drain contacts of the plurality of first source/drain contacts have a second width less than the first width;

a plurality of second source/drain contacts extending in the second direction and overlapping a plurality of second source/drain regions in a second active region of the plurality of active regions on opposite sides of the plurality of gate structures, wherein a first set of second source/drain contacts of the plurality of second source/drain contacts have the first width, and a second set of second source/drain contacts of the plurality of second source/drain contacts have the second width; and

a plurality of interconnect structures extending in the second direction, wherein each interconnect structure of the plurality of interconnect structures is electrically coupled to a corresponding first source/drain contact of the plurality of first source/drain contacts and a corresponding second source/drain contact of the plurality of second source/drain contacts.

8. The semiconductor device of claim 7, further comprising one or more isolation structures separating the plurality of active regions from one another.

9. The semiconductor device of claim 7, wherein at least one interconnect structure of the plurality of interconnect structures is in direct contact with the corresponding first source/drain contact of the plurality of first source/drain contacts and the corresponding second source/drain contact of the plurality of second source/drain contacts.

10. The semiconductor device of claim 7, further comprising a plurality of first vias coupling the plurality of interconnect structures to corresponding first source/drain contacts of the plurality of first source/drain contacts and a plurality of second vias coupling the plurality of interconnect structures to corresponding second source/drain contacts of the plurality of second source/drain contacts.

11. The semiconductor device of claim 10, wherein each interconnect structure of the plurality of interconnect structures is coupled to the corresponding first source/drain contact of the plurality of first source/drain contacts through a corresponding first via of the plurality of first vias, and to the corresponding second source/drain contact of the plurality of second source/drain contacts through a corresponding second via of the plurality of second vias.

12. The semiconductor device of claim 10, wherein a first set of first vias of the plurality of first vias contacting the first set of first source/drain contacts of the plurality of first source/drain contacts have a dimension greater than a dimension of a second set of first vias of the plurality of first vias contacting the second set of first source/drain contacts of the plurality of first source/drain contacts.

13. The semiconductor device of claim 10, wherein a first set of second vias of the plurality of second vias contacting the first set of second source/drain contacts of the plurality of second source/drain contacts have a dimension greater than a dimension of a second set of second vias of the plurality of second vias contacting the second set of second source/drain contacts of the plurality of second source/drain contacts.

14. The semiconductor device of claim 7, wherein adjacent gate structures of the plurality of gate structures have a uniform pitch.

15. The semiconductor device of claim 7, wherein the plurality of first source/drain regions comprises dopants of a first conductivity type, and the plurality of second source/drain regions comprises dopants of a second conductivity type.

16. The semiconductor device of claim 15, wherein the first conductivity is the same as the second conductivity type.

17. The semiconductor device of claim 15, wherein the first conductivity is different from the second conductivity type.

18. A system for processing a layout of a semiconductor device, comprising:

at least one processor; and

a computer readable storage medium connected to the at least one processor, wherein the at least one processor is configured to execute instructions stored on the computer readable storage medium to;

generate an active region layout pattern extending in a first direction,

generate a plurality of gate layout patterns extending in a second direction different from the first direction, wherein the plurality of gate layout patterns extends across the active region layout pattern;

generate a plurality of source/drain region layout patterns in the active region layout pattern on opposite sides of the plurality of gate layout patterns;

generate a plurality of source/drain contact layout patterns overlapping the plurality of source/drain region layout patterns; and

generate one or more mark layers, wherein each of one or more mark layers labels a corresponding source/drain contact layout pattern of the plurality of source/drain contact layout patterns and is usable to indicate the corresponding source/drain layout pattern of the plurality of source/drain contact layout patterns has a width greater than each source/drain layout pattern of the plurality of source/drain contact layout patterns that is not labeled by the one or more mark layers.

19. The system of claim 18, wherein the at least one processor is further configured to execute instructions on the computer readable storage medium to:

generate a conductive layer layout pattern electrically coupled to corresponding source/drain contact layout patterns of the plurality of source/drain contact layout patterns.

20. The system of claim 19, wherein the at least one processor is further configured to execute instructions on the computer readable storage medium to:

generate a plurality of via layout patterns, wherein the plurality of via layout patterns electrically couples the conductive layer layout pattern to the corresponding source/drain contact layout patterns of the plurality of source/drain contact layout patterns.