INTEGRATED CIRCUIT LAYOUTS WITH SOURCE AND DRAIN CONTACTS OF DIFFERENT WIDTHS
First Claim
1. A semiconductor device comprising:
- an active region in a substrate, wherein the active region extends in a first direction;
a gate structure extending in a second direction different from the first direction, wherein the gate structure extends across the active region; and
a plurality of source/drain contacts extending in the second direction and overlapping a plurality of source/drain regions in the active region on opposite sides of the gate structure, wherein a first source/drain contact of the plurality of source/drain contacts has a first width, and a second source/drain contact of the plurality of source/drain contacts has a second width less than the first width.
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Abstract
A semiconductor device includes an active region in a substrate. The active region extends in a first direction. The semiconductor device further includes a gate structure extending in a second direction different from the first direction. The gate structure extends across the active region. The semiconductor device further includes a plurality of source/drain contacts extending in the second direction and overlapping a plurality of source/drain regions in the active region on opposite sides of the gate structure. A first source/drain contact of the plurality of source/drain contacts has a first width, and a second source/drain contact of the plurality of source/drain contacts has a second width less than the first width.
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Citations
20 Claims
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1. A semiconductor device comprising:
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an active region in a substrate, wherein the active region extends in a first direction; a gate structure extending in a second direction different from the first direction, wherein the gate structure extends across the active region; and a plurality of source/drain contacts extending in the second direction and overlapping a plurality of source/drain regions in the active region on opposite sides of the gate structure, wherein a first source/drain contact of the plurality of source/drain contacts has a first width, and a second source/drain contact of the plurality of source/drain contacts has a second width less than the first width. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor device comprising:
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a plurality of active regions in a substrate, wherein each of the plurality of active regions extends in a first direction and is separated from one another in a second direction different from the first direction; a plurality of gate structures extending in the second direction, wherein each of the plurality of gate structures extends across each active region of the plurality of active regions; a plurality of first source/drain contacts extending in the second direction and overlapping a plurality of first source/drain regions in a first active region of the plurality of active regions on opposite sides of the plurality of gate structures, wherein a first set of first source/drain contacts of the plurality of first source/drain contacts have a first width, and a second set of first source/drain contacts of the plurality of first source/drain contacts have a second width less than the first width; a plurality of second source/drain contacts extending in the second direction and overlapping a plurality of second source/drain regions in a second active region of the plurality of active regions on opposite sides of the plurality of gate structures, wherein a first set of second source/drain contacts of the plurality of second source/drain contacts have the first width, and a second set of second source/drain contacts of the plurality of second source/drain contacts have the second width; and a plurality of interconnect structures extending in the second direction, wherein each interconnect structure of the plurality of interconnect structures is electrically coupled to a corresponding first source/drain contact of the plurality of first source/drain contacts and a corresponding second source/drain contact of the plurality of second source/drain contacts. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A system for processing a layout of a semiconductor device, comprising:
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at least one processor; and a computer readable storage medium connected to the at least one processor, wherein the at least one processor is configured to execute instructions stored on the computer readable storage medium to; generate an active region layout pattern extending in a first direction, generate a plurality of gate layout patterns extending in a second direction different from the first direction, wherein the plurality of gate layout patterns extends across the active region layout pattern; generate a plurality of source/drain region layout patterns in the active region layout pattern on opposite sides of the plurality of gate layout patterns; generate a plurality of source/drain contact layout patterns overlapping the plurality of source/drain region layout patterns; and generate one or more mark layers, wherein each of one or more mark layers labels a corresponding source/drain contact layout pattern of the plurality of source/drain contact layout patterns and is usable to indicate the corresponding source/drain layout pattern of the plurality of source/drain contact layout patterns has a width greater than each source/drain layout pattern of the plurality of source/drain contact layout patterns that is not labeled by the one or more mark layers. - View Dependent Claims (19, 20)
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Specification