Integrated Circuits Having Protruding Interconnect Conductors

• US 20200135871A1
• Filed: 02/20/2019
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Chen-Hung, Lee, Chen-Ming, Yang, Fu-Kai, Wang, Mei-Yun
• Granted Patent: US 10,943,983 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes an inter-level dielectric layer. A first contact that includes a fill material is formed that extends through the inter-level dielectric layer. The inter-level dielectric layer is recessed such that the fill material extends above a top surface of the inter-level dielectric layer. An etch-stop layer is formed on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer. A second contact is formed extending through the etch-stop layer to couple to the first contact. In some such examples, the second contact physically contacts a top surface and a side surface of the first contact.

Claims

1. A method of forming an integrated circuit device, the method comprising:

receiving a workpiece that includes an inter-level dielectric layer;

forming a first contact extending through the inter-level dielectric layer, wherein the first contact includes a fill material;

recessing the inter-level dielectric layer such that the fill material extends above a top surface of the inter-level dielectric layer;

forming an etch-stop layer on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer; and

forming a second contact extending through the etch-stop layer to couple to the first contact.

2. The method of claim 1, wherein the second contact physically contacts a top surface and a side surface of the first contact.

3. The method of claim 1, wherein the first contact further includes a liner and the fill material is disposed within the liner, the method further comprising:

recessing the liner such that the fill material extends above a top surface of the liner.

4. The method of claim 1, wherein the workpiece includes a source/drain feature, and wherein the forming of the first contact includes:

depositing a liner precursor within a recess in the inter-level dielectric layer; and

annealing the workpiece to form a liner and to form a silicide feature between the source/drain feature and the liner.

5. The method of claim 1, wherein the inter-level dielectric layer extends above a top surface of the fill material prior to the recessing of the inter-level dielectric layer.

6. The method of claim 1, wherein:

the workpiece includes a source/drain feature; and

the forming of the first contact includes forming a recess in the inter-level dielectric layer and in the source/drain feature.

7. The method of claim 6, wherein the recess has a depth such that the fill material extends below a top surface of the source/drain feature.

8. The method of claim 6, wherein the forming of the first contact further includes forming a dielectric liner on side surfaces of the recess.

9. The method of claim 8, wherein the dielectric liner extends into the source/drain feature.

10. A method comprising:

receiving a workpiece that includes a source/drain feature and an inter-level dielectric layer disposed on the source/drain feature;

forming a first contact extending through the inter-level dielectric layer to electrically couple to the source/drain feature;

recessing the inter-level dielectric layer such a top surface of the first contact is above a top surface of the inter-level dielectric layer; and

forming a second contact coupled to the first contact.

11. The method of claim 10, wherein the second contact physically contacts a top surface and a side surface of the first contact.

12. The method of claim 10 further comprising:

forming an etch-stop layer on the inter-level dielectric layer and on the first contact, wherein the first contact extends into the etch-stop layer, and wherein the second contact extends through the etch-stop layer to couple to the first contact.

13. The method of claim 12, wherein the etch-stop layer includes a mesa disposed over the first contact that extends above a remainder of the etch-stop layer.

14. The method of claim 10, wherein the first contact extends below a top surface of the source/drain feature.

15. The method of claim 10, wherein the forming of the first contact includes:

depositing a liner precursor on the inter-level dielectric layer and on the source/drain feature; and

annealing the workpiece to form a liner and to form a silicide feature between the source/drain feature and the first contact.

16. The method of claim 10, wherein the inter-level dielectric layer extends above a top surface of the first contact prior to the recessing of the inter-level dielectric layer.

17. An integrated circuit device comprising:

a substrate;

an inter-level dielectric disposed on the substrate;

a first contact extending through the inter-level dielectric, wherein the first contact extends above the inter-level dielectric; and

a second contact in physical contact with a top surface of the first contact.

18. The integrated circuit device of claim 17, wherein the second contact is further in physical contact with a side surface of the first contact.

19. The integrated circuit device of claim 17, wherein the second contact extends beyond the first contact to physically contact the inter-level dielectric.

20. The integrated circuit device of claim 17, wherein the first contact includes a liner and a contact fill disposed within the liner, wherein the contact fill extends above a topmost surface of the liner.