DEVICE VARIATION CONTROL OF VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTOR DEVICES BY SELECTIVE OXIDE DEPOSITION FOR SHALLOW TRENCH ISOLATION FORMATION

• US 20200135873A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wu, Heng, Cheng, Kangguo, Zhang, Chen, Yamashita, Tenko, Mehta, Sanjay C.
• Application Number:
  US16/174,906
• Publication Number:
  US 20200135873A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A method of forming an isolation region is provided. The method includes forming a bottom source/drain layer on a substrate, forming an isolation trench through the bottom source/drain layer into the substrate, and filling the isolation trench using a selective oxide deposition, wherein the top surface of the deposited oxide is aligned with a top edge of the bottom source/drain layer.

Claims

1. A method of forming an isolation region, comprising:

forming a bottom source/drain layer on a substrate, wherein the substrate and the bottom source/drain layer include a semiconductor material;

forming an isolation trench through the bottom source/drain layer into the substrate; and

filling the isolation trench using a selective oxide deposition, wherein the oxide is selectively deposited on the surfaces of the semiconductor materials but not non-semiconductor materials, and the top surface of the deposited oxide is aligned with a top edge of the bottom source/drain layer.

2. The method of claim 1, further comprising forming a bottom spacer layer on the bottom source/drain layer, wherein the isolation trench goes through the bottom spacer layer.

3. The method of claim 2, wherein the bottom spacer layer is a dielectric material, and wherein the selective oxide deposition selectively forms silicon oxide on the exposed surfaces of the semiconductor materials and not the dielectric material.

4. The method of claim 1, further comprising forming a plurality of vertical fins on the substrate, and foil ling a fin liner on the plurality of vertical fins.

5. The method of claim 4, further comprising forming a protective layer on the bottom source/drain layer and the fin liner, and removing a portion of the protective layer to expose a portion of the underlying bottom source/drain layer.

6. The method of claim 5, wherein the isolation trench extends through the expose portion of the underlying bottom source/drain layer into the substrate.

7. The method of claim 6, wherein the fin liner is a hardmask material selected from the group consisting of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon borocarbide (SiBC), silicon boro carbonitride (SiBCN), and combinations thereof.

8. The method of claim 5, further comprising forming a silicon oxide material on the exposed surfaces of the bottom source/drain layer using the selective oxide deposition.

9. The method of claim 8, further comprising removing the silicon oxide material from the bottom source/drain layer using a selective isotropic etch, wherein a portion of the silicon oxide material remains in the isolation trench.

10. The method of claim 1, further comprising forming a shielding liner on the exposed surfaces of the isolation trench, and removing a portion of the shielding liner from the bottom surface of the isolation trench.

11. A method of forming an isolation region, comprising:

forming two or more vertical fins on a semiconductor substrate, wherein a separate fin template is on a top surface of each of the two or more vertical fins;

forming a bottom source/drain layer on the semiconductor substrate, wherein the bottom source/drain layer is a semiconductor material;

forming a fin liner on the sidewalls of the two or more vertical fins;

forming a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer is a dielectric material;

forming an isolation trench through the bottom spacer layer and the bottom source/drain layer into the semiconductor substrate between two of the two or more vertical fins; and

filling the isolation trench using a selective oxide deposition that deposits a silicon oxide (SiO) on the exposed surfaces of the semiconductor materials but not non-semiconductor materials.

12. The method of claim 11, wherein the substrate and bottom source/drain layer are single crystal silicon, and the bottom spacer layer is a dielectric material selected from the group consisting of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon borocarbide (SiBC), silicon boro carbonitride (SiBCN), and combinations thereof.

13. The method of claim 12, wherein the fin liner is a hardmask material selected from the group consisting of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon borocarbide (SiBC), silicon boro carbonitride (SiBCN), and combinations thereof, wherein the fin liner is a different hardmask material from the bottom spacer layer.

14. The method of claim 13, further comprising forming a gate structure on the two or more vertical fins.

15. The method of claim 14, further comprising forming a dielectric separation region that physically and electrically separates the gate structure into two adjacent gate structures.

16. A vertical transport fin field effect transistor device, comprising:

two vertical fins on a substrate;

a bottom source/drain layer on the substrate;

a bottom spacer layer on the bottom source/drain layer;

an isolation trench between the two vertical fins, wherein the isolation trench extends through the bottom spacer layer and the bottom source/drain layer; and

a dielectric fill in the isolation trench, wherein the dielectric fill fills the isolation trench up to the bottom edge of the bottom spacer layer, such that a gap remains between adjacent sections of the bottom spacer layer.

17. The vertical transport fin field effect transistor device of claim 16, further comprising a gate structure on the two vertical fins, and a dielectric separation region that physically and electrically separates the gate structure into two adjacent gate structures.

18. The vertical transport fin field effect transistor device of claim 16, wherein the substrate and bottom source/drain layer are single crystal silicon, and the bottom spacer layer is a dielectric material selected from the group consisting of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon borocarbide (SiBC), silicon boro carbonitride (SiBCN), and combinations thereof.

19. The vertical transport fin field effect transistor device of claim 18, further comprising a top spacer layer on the two adjacent gate structures.

20. The vertical transport fin field effect transistor device of claim 19, further comprising a top source/drain on each of the two vertical fins.