STRUCTURES AND METHODS FOR NOISE ISOLATION IN SEMICONDUCTOR DEVICES

• US 20200135875A1
• Filed: 12/30/2019
• Published: 04/30/2020
• Est. Priority Date: 11/21/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: SINGH, Gulbagh, TSAI, Tsung-Han, CHUANG, Kun-Tsang
• Granted Patent: US 11,183,570 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

The present disclosure relates to a semiconductor structure includes a substrate with a top surface and first and second devices formed on the top surface of the substrate. The semiconductor structure also includes a deep isolation structure formed in the substrate and between the first and second devices. The deep isolation structure includes a top portion formed at the top surface and having a top width and a bottom surface having a bottom width larger than the top width.

Claims

1. A semiconductor structure, comprising:

a substrate with a top surface;

first and second devices formed on the top surface of the substrate; and

an isolation structure between the first and second devices, wherein the isolation structure comprises;

a top portion formed at the top surface and having a top width;

a bottom surface having a bottom width larger than the top width; and

an air pocket extending through the isolation structure, wherein the air pocket comprises a first width at the top surface of the substrate and a second width at the bottom surface of the isolation structure, wherein the second width is larger than the first width.

2. The semiconductor structure of claim 1, wherein the isolation structure further comprises a first portion comprising a first material with a first dielectric constant and a second portion comprising a second material with a second dielectric constant lower than the first dielectric constant.

3. The semiconductor structure of claim 1, wherein the substrate comprises a silicon-on-insulator (SOI) substrate.

4. The semiconductor structure of claim 1, wherein the isolation structure comprises a sidewall, wherein a first angle between the sidewall and the top surface of the substrate is greater than about 90°

.

5. The semiconductor structure of claim 4, wherein a second angle between the sidewall and the bottom surface is less than about 90°

.

6. The semiconductor structure of claim 1, wherein a ratio of the top width to the bottom width is between about 0.6 and about 0.95.

7. The semiconductor structure of claim 1, wherein the isolation structure further comprises a dielectric material structure.

8. The semiconductor structure of claim 1, wherein a ratio of the first width to the second first width is between about 5% and about 30%.

9. The semiconductor structure of claim 1, wherein a volume of the air pocket is between about 30% and about 80% of a total volume of the isolation structure.

10. The semiconductor structure of claim 8, wherein the air pocket comprises an other bottom surface which contours the bottom surface of the isolation structure.

11. A semiconductor structure, comprising:

a substrate;

a first dielectric layer formed on the substrate;

a second dielectric layer formed on the first dielectric layer, wherein the second dielectric layer comprises top and bottom surfaces;

a device layer on the second dielectric layer;

first and second semiconductor devices formed on the device layer; and

an isolation structure formed in the substrate and the first and second dielectric layers, wherein the isolation structure comprises;

a top width measured at the top surface of the second dielectric layer;

a bottom width measured at a bottom surface of the isolation structure, wherein the top width is less than the bottom width; and

an air pocket extending through the bottom surface of the second dielectric layer.

12. The semiconductor structure of claim 11, wherein the isolation structure further comprises a first portion comprising a first material with a first dielectric constant and a second portion comprising a second material with a second dielectric constant.

13. The semiconductor structure of claim 12, wherein the first dielectric constant is a low-k dielectric constant.

14. The semiconductor structure of claim 13, wherein the second dielectric constant is about 1.

15. The semiconductor structure of claim 12, wherein the air pocket has a first width at the top surface of the second dielectric layer and a second width at the bottom surface of the isolation structure, wherein the second width is larger than the first width.

16. A method for forming a semiconductor device, comprising:

providing a substrate;

forming first and second devices on the substrate;

etching at least one trench in the substrate and between the first and second devices, wherein a top opening of the at least one trench is narrower than a bottom surface of the trench; and

depositing a dielectric material between the first and second devices and in the at least one trench, wherein;

the deposited dielectric material forms an air pocket in the at least one trench; and

the air pocket comprises a top portion with a top width and a bottom portion with a bottom width, wherein the bottom width is larger than the top width.

17. The method of claim 16, wherein the etching comprises etching one or more dielectric layers of the substrate.

18. The method of claim 16, wherein a ratio of the top width to the bottom width is between about 5% and 30%.

19. The method of claim 16, wherein the depositing comprises depositing the dielectric material using a physical vapor deposition method.

20. The method of claim 16, wherein the etching comprises etching the at least one trench using a wet chemical etching method.