SEMICONDUCTOR DEVICE

• US 20200135876A1
• Filed: 01/02/2020
• Published: 04/30/2020
• Est. Priority Date: 07/07/2017
• Status: Active Grant

• Current Assignee: Osaka University, Panasonic Holdings Corporation
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Shih, Hong-An, Nakazawa, Satoshi, Tsurumi, Naohiro, Anda, Yoshiharu, Watanabe, Heiji, Shimura, Takayoshi, Hosoi, Takuji, Nozaki, Mikito, Yamada, Takahiro
• Granted Patent: US 11,342,428 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/7789 the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor device including: a metal-insulator-semiconductor (MIS) structure that includes a nitride semiconductor layer, a gate insulator film, and a gate electrode stacked in stated order; and a source electrode and a drain electrode that are disposed to sandwich the gate electrode in a plan view and contact the nitride semiconductor layer. The gate insulator film includes a threshold value control layer that includes an oxynitride film.

Claims

1. A semiconductor device, comprising:

a metal-insulator-semiconductor (MIS) structure that includes a nitride semiconductor layer, a gate insulator film, and a gate electrode stacked in stated order; and

a source electrode and a drain electrode that are disposed to sandwich the gate electrode in a plan view and contact the nitride semiconductor layer, wherein

the gate insulator film includes a threshold value control layer that includes an oxynitride film.

2. The semiconductor device according to claim 1, wherein

the threshold value control layer contains aluminum.

3. The semiconductor device according to claim 1, wherein

a nitrogen composition ratio of the threshold value control layer is at least 3 at. % and at most 25 at. %.

4. The semiconductor device according to claim 3, wherein

the nitrogen composition ratio of the threshold value control layer is at least 3 at. % and at most 15 at. %.

5. The semiconductor device according to claim 3, wherein

the nitrogen composition ratio of the threshold value control layer is at least 3 at. % and at most 12 at. %.

6. The semiconductor device according to claim 1, wherein

the threshold value control layer is amorphous or microcrystalline.

7. The semiconductor device according to claim 1, wherein

a nitrogen content in the threshold value control layer decreases from the nitride semiconductor layer toward the gate electrode.

8. The semiconductor device according to claim 1, wherein

the gate insulator film further includes a first insulation layer that is stacked on the threshold value control layer at a side of the gate electrode and includes one of an oxide film, a nitride film, or an oxynitride film.

9. The semiconductor device according to claim 1, wherein

the gate insulator film further includes a second insulation layer that is stacked on the threshold value control layer at a side of the nitride semiconductor layer and includes one of an oxide film, a nitride film, or an oxynitride film.

10. The semiconductor device according to claim 1, wherein

the gate insulator film further includes:

a first insulation layer that is stacked on the threshold value control layer at a side of the gate electrode and includes one of an oxide film, a nitride film, or an oxynitride film; and

a second insulation layer that is stacked on the threshold value control layer at a side of the nitride semiconductor layer and includes one of an oxide film, a nitride film, or an oxynitride film.

11. The semiconductor device according to claim 1, wherein

the nitride semiconductor layer has a stacked structure of GaN and Al_xGa₁₋

xN, where 0≤

x≤

1.

12. The semiconductor device according to claim 1, wherein

a gate recess is disposed in the nitride semiconductor layer.

13. The semiconductor device according to claim 12, wherein

the nitride semiconductor layer includes:

a first nitride semiconductor layer; and

a second nitride semiconductor layer that is stacked on the first nitride semiconductor layer at a side of the gate electrode and includes the gate recess, and

the first nitride semiconductor layer includes a recess that is disposed at a position overlapping the gate recess in the plan view and is recessed from the gate electrode toward the nitride semiconductor layer.

14. The semiconductor device according to claim 13, wherein

the second nitride semiconductor layer has a uniform film thickness along an inner surface of the recess.

15. The semiconductor device according to claim 1, further compising:

a spacer layer disposed between the nitride semiconductor layer and the gate insulator film, wherein

the spacer layer is located between the gate electrode and the source electrode and between the gate electrode and the drain electrode in the plan view.

16. The semiconductor device according to claim 15, wherein

a portion of the spacer layer overlaps the gate electrode in the plan view.

17. The semiconductor device according to claim 1, wherein

the gate insulator film is not disposed in at least a portion between the gate electrode and the source electrode and between the gate electrode and the drain electrode in the plan view.