SELF-ALIGNED GATE CUT IN DIRECT STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR (VTFET)
First Claim
1. A semiconductor structure, comprising:
- a silicon on insulator (SOI) semiconductor fin comprising a dielectric fin extension;
a first vertical transport field effect transistor (VTFET) comprising a first self-aligned gate on the dielectric fin extension;
a second VTFET comprising a second self-aligned gate on the dielectric fin extension; and
a gate contact extending through the dielectric fin extension through the second VTFET to the first self-aligned gate.
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Accused Products
Abstract
Structures and/or methods that facilitate self-aligned gate cut on a dielectric fin extension in direct stacked vertical transport field effect transistor (VTFET). A semiconductor structure can comprise a silicon on insulator (SOI) semiconductor fin comprising a dielectric fin extension. The semiconductor structure can further comprise a first vertical transport field effect transistor (VTFET) comprising a first self-aligned gate on the dielectric fin extension. The semiconductor structure can further comprise a second VTFET comprising a second self-aligned gate on the dielectric fin extension. The semiconductor structure can further comprise a gate contact extending through the dielectric fin extension through the second VTFET to the first self-aligned gate.
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Citations
20 Claims
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1. A semiconductor structure, comprising:
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a silicon on insulator (SOI) semiconductor fin comprising a dielectric fin extension; a first vertical transport field effect transistor (VTFET) comprising a first self-aligned gate on the dielectric fin extension; a second VTFET comprising a second self-aligned gate on the dielectric fin extension; and a gate contact extending through the dielectric fin extension through the second VTFET to the first self-aligned gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method, comprising:
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forming a silicon on insulator (SOI) semiconductor fin comprising a dielectric fin extension; forming a first vertical transport field effect transistor (VTFET) comprising a first self-aligned gate on the dielectric fin extension; forming a second VTFET comprising a second self-aligned gate on the dielectric fin extension; and forming a gate contact extending through the dielectric fin extension through the second VTFET to the first self-aligned gate. - View Dependent Claims (17, 18)
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19. A method, comprising:
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forming a dielectric fin extension on a silicon on insulator (SOI) wafer; forming a first vertical transport field effect transistor (VTFET) and a second VTFET on an SOI semiconductor fin comprising the dielectric fin extension; and forming a gate contact extending through the dielectric fin extension through the second VTFET to a self-aligned gate of the first VTFET. - View Dependent Claims (20)
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Specification