Gate Structure and Patterning Method for Multiple Threshold Voltages

• US 20200135879A1
• Filed: 03/25/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Chung-Liang, Fang, Ziwei
• Granted Patent: US 10,770,563 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of fins disposed over the semiconductor substrate, the plurality of fins comprising a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions; and

a plurality of gate structures comprising;

an interfacial layer (IL) disposed over the plurality of channel regions;

a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region;

a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and

a third high-k dielectric layer disposed over the plurality of channel regions, wherein the first, second and third high-k dielectric layers are different from one another.

2. The semiconductor device of claim 1,

wherein the first high-k dielectric layer has a first thickness, the second high-k dielectric layer has a second thickness, and the third high-k dielectric layer has a third thickness,

wherein the third thickness is greater than the second thickness and the second thickness is greater than the first thickness.

3. The semiconductor device of claim 1,

wherein the first high-k dielectric layer comprises aluminum,

wherein the third high-k dielectric layer comprises lanthanum.

4. The semiconductor device of claim 1,

wherein, over the first p-type channel region and the first n-type channel region, the second high-k dielectric layer is disposed between the first high-k dielectric layer and the third high-k dielectric layer,

wherein, over the third n-type channel region and the third p-type channel region, the third high-k dielectric layer is in contact with the interfacial layer.

5. The semiconductor device of claim 1, wherein the plurality of gate structures further comprises:

a capping layer disposed over the third high-k dielectric layer over the plurality of channel regions;

a barrier layer disposed over the capping layer over the plurality of channel regions;

an n-type work function layer disposed over the capping layer over the plurality of channel regions; and

over the first, second and third p-type channel regions, a p-type work function layer disposed between the n-type work function layer and the barrier layer.

6. The semiconductor device of claim 5,

wherein the capping layer comprises titanium, silicon and nitrogen,

wherein the barrier layer comprises tantalum and nitrogen.

7. The semiconductor device of claim 5, further comprising:

a glue layer directly on the n-type work function layer over the plurality of channel regions; and

a fill metal material over the glue layer.

8. The semiconductor device of claim 1,

wherein the first n-type channel region comprises a first threshold voltage, the second n-type channel region comprises a second threshold voltage, and the third n-type channel region comprises a third threshold voltage,

wherein the first threshold voltage is greater than the second threshold voltage and the second threshold voltage is greater than the third threshold voltage.

9. The semiconductor device of claim 1,

wherein the first p-type channel region comprises a fourth threshold voltage, the second p-type channel region comprises a fifth threshold voltage, and the third p-type channel region comprises a sixth threshold voltage,

wherein the sixth threshold voltage is greater than the fifth threshold voltage and the fifth threshold voltage is greater than the fourth threshold voltage.

10. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of fins disposed over the semiconductor substrate, the plurality of fins comprising a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions; and

a plurality of gate structures comprising;

an interfacial layer (IL) disposed over the plurality of channel regions;

a first high-k (HK) dielectric layer disposed on the interfacial layer over the first n-type channel region and the first p-type channel region;

a second high-k dielectric layer disposed on the first high-k dielectric layer disposed over the first n-type channel region and the first p-type channel region, and on the interfacial layer disposed over the second n-type channel region and the second p-type channel region; and

a third high-k dielectric layer disposed on the second high-k dielectric layer disposed over the first n-type channel region, the first p-type channel region, the second n-type channel region, the second p-type channel region, and on the interfacial layer disposed over the third n-type channel region and the third p-type channel region, wherein the first, second and third high-k dielectric layers are different from one another.

11. The semiconductor device of claim 10,

wherein the first high-k dielectric layer has a first thickness, the second high-k dielectric layer has a second thickness, and the third high-k dielectric layer has a third thickness,

wherein the third thickness is greater than the second thickness and the second thickness is greater than the first thickness.

12. The semiconductor device of claim 10,

wherein the first high-k dielectric layer comprises aluminum,

wherein the third high-k dielectric layer comprises lanthanum.

13. The semiconductor device of claim 10, wherein the plurality of gate structures further comprises:

a capping layer disposed over the third high-k dielectric layer over the plurality of channel regions;

a barrier layer disposed over the capping layer over the plurality of channel regions;

an n-type work function layer disposed over the capping layer over the plurality of channel regions; and

over the first, second and third p-type channel regions, a p-type work function layer disposed between the n-type work function layer and the barrier layer,

wherein the capping layer comprises titanium, silicon and nitrogen,

wherein the barrier layer comprises tantalum and nitrogen.

14. The semiconductor device of claim 10,

wherein the first n-type channel region comprises a first threshold voltage, the second n-type channel region comprises a second threshold voltage, and the third n-type channel region comprises a third threshold voltage,

wherein the first threshold voltage is greater than the second threshold voltage and the second threshold voltage is greater than the third threshold voltage.

15. The semiconductor device of claim 10,

wherein the first p-type channel region comprises a fourth threshold voltage, the second p-type channel region comprises a fifth threshold voltage, and the third p-type channel region comprises a sixth threshold voltage,

wherein the sixth threshold voltage is greater than the fifth threshold voltage and the fifth threshold voltage is greater than the fourth threshold voltage.

16. A method, comprising:

providing a workpiece including a semiconductor substrate, a plurality of fins disposed over the semiconductor substrate, the plurality of fins comprising a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions; and

forming a plurality of gate structures over the plurality of channel regions, comprising;

forming an interfacial layer over the plurality of channel regions,

selectively forming a first high-k dielectric layer over the interfacial layer over the first n-type channel region and the first p-type channel region,

selectively forming a second high-k dielectric layer over the interfacial layer over the second n-type channel region and the second p-type channel region, and over the first high-k dielectric layer over the first n-type channel region and the first p-type channel region,

forming a third high-k dielectric layer over the second high-k dielectric layer disposed over the first n-type channel region, the first p-type channel region, the second n-type channel region, the second p-type channel region, and over the interfacial layer disposed over the third n-type channel region and the third p-type channel region,

selectively forming a p-type work function layer over the first, second and third p-type channel regions,

forming an n-type work function layer over the plurality of channel regions, and

forming a fill metal layer over the plurality of channel regions,

wherein the first, second and third high-k dielectric layers are different from one another.

17. The method of claim 16, wherein the selectively forming of the first high-k dielectric layer comprises:

depositing the first high-k dielectric layer over the plurality of channel regions;

depositing a metal nitride hard mask over the first high-k dielectric layer;

patterning the metal nitride hard mask by removing the metal nitride hard mask over the second n-type channel region, the third n-type channel region, the third n-type channel region, the second p-type channel region, and the third p-type channel region; and

recessing the deposited first high-k dielectric layer using the patterned metal nitride hard mask layer as an etch mask.

18. The method of claim 17, wherein the metal nitride hard mask comprises titanium, tantalum, tungsten.

19. The method of claim 16, further comprising:

depositing a capping layer over the third high-k dielectric layer over the plurality of channel regions;

depositing a barrier layer over the capping layer over the plurality of channel regions;

forming a p-type work function layer over the first, second and third p-type channel regions; and

forming an n-type work function layer over the plurality of channel regions,

wherein the capping layer comprises titanium, silicon and nitrogen,

wherein the barrier layer comprises tantalum and nitrogen.

20. The method of claim 16,

wherein the selectively forming of the first high-k dielectric layer comprises forming the first high-k dielectric layer to a first thickness,

wherein the selectively forming of the second high-k dielectric layer comprises forming the second high-k dielectric layer to a second thickness,

wherein the selectively forming the third high-k dielectric layer comprises forming the third high-k dielectric layer to a third thickness,

wherein the third thickness is greater than the second thickness and the second thickness is greater than the first thickness.