SELF-ALIGNED CONTACT WITH METAL-INSULATOR TRANSISTION MATERIALS

• US 20200135881A1
• Filed: 10/24/2018
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: LEE, CHOONGHYUN, Cheng, Kangguo, LI, JUNTAO, XU, PENG
• Granted Patent: US 10,978,571 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

Embodiments of the present invention are directed to techniques for forming a self-aligned contact liner using metal-insulator transition materials. The self-aligned contact architecture described herein prevents a short between the gate and the source/drain, even when the self-aligned contact (SAC) cap has eroded to the point where the gate is exposed. In a non-limiting embodiment of the invention, a dielectric cap is formed over a conductive gate. A source or drain region is formed adjacent to the conductive gate. A dielectric liner is formed over the dielectric cap and the source or drain region such that a first portion of the dielectric liner is on a surface of the source or drain region. The dielectric liner includes a metal-insulator transition material. The first portion of the dielectric liner is metalized via germanium oxide sublimation.

Claims

1. A method for forming a semiconductor device, the method comprising:

forming a dielectric cap over a conductive gate;

forming a source or drain (S/D) region adjacent to the conductive gate;

forming a dielectric liner over the dielectric cap and the (S/D) region such that a first portion of the dielectric liner is on a surface of the (S/D) region, the dielectric liner comprising a metal-insulator transition material; and

metalizing the first portion of the dielectric liner.

2. The method of claim 1, wherein metalizing the first portion of the dielectric liner comprises annealing the semiconductor device at a temperature of about 500 degrees Celsius.

3. The method of claim 1, wherein the metal-insulator transition material comprises metal-doped germanium oxide (M-GeO_x).

4. The method of claim 3, wherein the metal-doped germanium oxide is metalized on the surface of the source or drain region according to the formula:

2M-GeO_x+Si+Ge→

2GeO(volatile)+M-Si(silicide)+M-Ge(germanide) 

 

(I)

5. The method of claim 3, wherein the metal-doped germanium oxide comprises a metal dopant having a concentration of about 5 to about 30 percent.

6. The method of claim 5, wherein the metal dopant comprises yttrium (Y), scandium (Sc), hafnium (Hf), titanium (Ti), aluminum (Al), or lanthanum (La).

7. The method of claim 1, wherein the dielectric cap comprises a self-aligned contact cap.

8. The method of claim 1, wherein a second portion of the dielectric liner is on a surface of the conductive gate.

9. The method of claim 1, wherein the source or drain region comprises silicon germanium having a germanium concentration of about 10 percent to about 65 percent.

10. A method for forming a semiconductor device, the method comprising:

conformally forming a metal-insulator transition material on a surface of a conductive gate and on a surface of a (S/D) region; and

selectively metalizing a portion of the metal-insulator transition material in contact with the surface of the (S/D) region.

11. The method of claim 10, wherein selectively metalizing the portion of the metal-insulator transition material further comprises a germanium oxide sublimation.

12. The method of claim 11, wherein germanium oxide sublimation occurs on the surface of the source or drain region according to the formula:

2M-GeO_x+Si+Ge→

2GeO(volatile)+M-Si(silicide)+M-Ge(germanide) 

 

(I)

13. The method of claim 10, wherein the metal-insulator transition material comprises metal-doped germanium oxide (M-GeO_x).

14. The method of claim 13, wherein the metal-doped germanium oxide comprises a metal dopant having a concentration of about 5 to about 30 percent.

15. The method of claim 14, wherein the metal dopant comprises yttrium (Y), scandium (Sc), hafnium (Hf), titanium (Ti), aluminum (Al), or lanthanum (La).

16. The method of claim 10, wherein the (S/D) region comprises silicon germanium having a germanium concentration of about 10 percent to about 65 percent.

17. A semiconductor device comprising:

a dielectric cap over a conductive gate;

a (S/D) region adjacent to the conductive gate; and

a conformal liner formed adjacent to a sidewall of the dielectric cap and on the (S/D) region;

wherein a first portion of the conformal liner is on a surface of the conductive gate, the first portion comprising a metal-doped germanium oxide; and

wherein a second portion of the conformal liner is on the (S/D) region, the second portion comprising a silicide or a germanide.

18. The semiconductor device of claim 17, wherein the metal-doped germanium oxide comprises a metal dopant having a concentration of about 5 to about 30 percent.

19. The semiconductor device of claim 18, wherein the metal dopant comprises yttrium (Y), scandium (Sc), hafnium (Hf), titanium (Ti), aluminum (Al), or lanthanum (La).

20. The semiconductor device of claim 17, wherein the conformal liner further comprises a thickness of about 0.2 to 10 nm.