NON-SELF ALIGNED GATE CONTACTS FORMED OVER THE ACTIVE REGION OF A TRANSISTOR
First Claim
1. A method for forming a silicon structure, the method comprising:
- forming a trench silicide contact between two spacers, each spacer beside respective high-k metal gates;
planarizing the trench silicide contact, the spacers, and the high-k metal gates;
depositing an inner layer dielectric over the trench silicide contact, the spacers, and the high-k metal gates;
patterning a first opening in the inner layer dielectric for a gate contact over the high-k metal gate, one of the spacers and a portion of the trench silicide contact;
recessing the portion of the trench silicide contact;
depositing a liner within the recessed portion of the trench silicide contact and on sidewalls of the first opening of the inner layer dielectric; and
depositing a metallization layer in the opening in the inner layer dielectric to form the gate contact.
1 Assignment
0 Petitions
Accused Products
Abstract
A method for forming a silicon structure. The method includes forming a trench silicide contact between two spacers, each spacer beside respective high-k metal gates. The method planarizes the trench silicide contact, the spacers, and the high-k metal gates. An inner layer dielectric is deposited over the trench silicide contact, the spacers, and the high-k metal gates. A first opening is patterned in the inner layer dielectric for a gate contact over the high-k metal gate, one of the spacers and a portion of the trench silicide contact. The method recesses the portion of the trench silicide contact and deposits a liner within the recessed portion of the trench silicide contact and on sidewalls of the first opening of the inner layer dielectric. A metallization layer is deposited in the opening in the inner layer dielectric to form the gate contact.
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Citations
20 Claims
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1. A method for forming a silicon structure, the method comprising:
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forming a trench silicide contact between two spacers, each spacer beside respective high-k metal gates; planarizing the trench silicide contact, the spacers, and the high-k metal gates; depositing an inner layer dielectric over the trench silicide contact, the spacers, and the high-k metal gates; patterning a first opening in the inner layer dielectric for a gate contact over the high-k metal gate, one of the spacers and a portion of the trench silicide contact; recessing the portion of the trench silicide contact; depositing a liner within the recessed portion of the trench silicide contact and on sidewalls of the first opening of the inner layer dielectric; and depositing a metallization layer in the opening in the inner layer dielectric to form the gate contact. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A semiconductor structure comprising:
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a substrate; a fin comprising a high-k metal gate with spacers on either side of the high-k metal gate on the substrate; a trench silicide, having a recess on the top of the trench silicide, on the substrate adjacent to one of the spacers; an inner layer dielectric over the fin and the trench silicide; a gate contact disposed within the inner layer dielectric above the high-k metal gate, one of the spacers, and the recess in the trench silicide; and a liner disposed on either side of the gate contact and within the recess in the top of the trench silicide. - View Dependent Claims (16, 17, 18)
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19. A semiconductor structure comprising:
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a substrate; a first fin comprising a first high-k metal gate with first and second spacers on either side of the first high-k metal gate on the substrate; a first trench silicide, having a recess on the top of the trench silicide, on the substrate adjacent to the first spacer; an inner layer dielectric over the first fin and the first trench silicide; a first gate contact disposed within the inner layer dielectric above the first high-k metal gate, the first spacer, and the recess in the first trench silicide; a first liner disposed on either side of the first gate contact and within the recess in the top of the trench silicide; a second fin comprising a second high-k metal gate with third and fourth spacers on either side of the second high-k metal gate on the substrate; an inner layer dielectric over the second fin; a second gate contact disposed within the inner layer dielectric above the second high-k metal gate and the third spacer; and a second liner disposed on either side of the second gate contact. - View Dependent Claims (20)
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Specification