DIELECTRIC CONSTANT REDUCTION OF GATE SPACER

• US 20200135887A1
• Filed: 10/03/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WU, Xu-Sheng, LIU, Chang-Miao, SHANG, Hui-Ling
• Granted Patent: US 11,075,283 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/3115 Doping the insulating layers
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method includes forming a dummy gate structure over a substrate, forming a plurality of gate spacers respectively on opposite sidewalls of the dummy gate structure and having a first dielectric constant, removing the dummy gate structure to form a gate trench between the gate spacers, forming a dopant source layer to line the gate trench, annealing the dopant source layer to diffuse k-value reduction impurities from the dopant source layer into the gate spacers to lower the first dielectric constant of the gate spacers to a second dielectric constant, and forming a replacement gate stack in the gate trench.

Claims

1. A method, comprising:

forming a dummy gate structure over a substrate;

forming a plurality of gate spacers respectively on opposite sidewalls of the dummy gate structure, the gate spacers having a first dielectric constant;

removing the dummy gate structure to form a gate trench between the gate spacers;

forming a dopant source layer to line the gate trench;

annealing the dopant source layer to diffuse k-value reduction impurities from the dopant source layer into the gate spacers to lower the first dielectric constant of the gate spacers to a second dielectric constant; and

forming a replacement gate stack in the gate trench.

2. The method of claim 1, further comprising:

removing the dopant source layer from the gate trench prior to forming the replacement gate stack.

3. The method of claim 2, wherein removing the dopant source layer is performed using an etchant same as an etchant used in removing the dummy gate structure.

4. The method of claim 2, wherein an etch duration of removing the dopant source layer is shorter than an etch duration of removing the dummy gate structure.

5. The method of claim 2, further comprising:

forming a gate dielectric layer over the substrate prior to forming the dummy gate structure, wherein the gate dielectric layer remains over the substrate after removing the dopant source layer.

6. The method of claim 5, further comprising:

removing the gate dielectric layer prior to forming the replacement gate stack.

7. The method of claim 1, wherein a material of the dopant source layer is same as a material of the dummy gate structure.

8. The method of claim 1, where the k-value reduction impurities are fluorine.

9. The method of claim 1, wherein the dopant source layer comprises polysilicon.

10. A method, comprising:

forming a first gate dielectric layer over a substrate and a first dummy gate structure over the first gate dielectric layer;

forming a plurality of first gate spacers alongside the first dummy gate structure;

etching the first dummy gate structure to form a first gate trench between the first gate spacers;

forming a dopant source layer over the first gate dielectric layer after etching the first dummy gate structure;

annealing the dopant source layer such that first k-value reduction impurities in the dopant source layer are diffused into the first gate dielectric layer; and

forming a first replacement gate stack in the first gate trench.

11. The method of claim 10, further comprising:

removing the first gate dielectric layer from the first gate trench prior to forming the first replacement gate stack.

12. The method of claim 10, further comprising:

forming a second gate dielectric layer over the substrate and a second dummy gate structure over the second gate dielectric layer;

forming a plurality of second gate spacers alongside the second dummy gate structure;

etching the second dummy gate structure to form a second gate trench between the second gate spacers, wherein the second gate dielectric layer remains over the substrate after etching the second dummy gate structure;

removing the first gate dielectric layer, wherein the second gate dielectric layer remains over the substrate after removing the first gate dielectric layer; and

forming a second replacement gate stack over the second gate dielectric layer.

13. The method of claim 12, further comprising:

prior to removing the first gate dielectric layer, forming a patterned mask to cover the second gate dielectric layer and expose the first gate dielectric layer; and

removing the patterned mask prior to forming the second replacement gate stack.

14. The method of claim 12, wherein annealing the dopant source layer is performed such that second k-value reduction impurities in the dopant source layer are diffused into the second gate dielectric layer.

15. The method of claim 12, wherein forming the dopant source layer is performed such that the dopant source layer is further formed over the second gate dielectric layer.

16. The method of claim 10, wherein forming the dopant source layer comprises:

depositing a polysilicon layer over the first gate dielectric layer; and

doping the polysilicon layer with fluorine.

17. The method of claim 16, wherein doping the polysilicon layer is in-situ performed with depositing the polysilicon layer.

18. A semiconductor device, comprising:

a substrate;

a gate stack over the substrate; and

a gate spacer on a sidewall of the gate stack, the gate spacer comprising an outer spacer and an inner spacer between the gate stack and the outer spacer, wherein the outer spacer and the inner spacer have same k-value reduction impurities, and a concentration of the k-value reduction impurities in the inner spacer is higher than a concentration of the k-value reduction impurities in the outer spacer.

19. The semiconductor device of claim 18, further comprising:

an interfacial layer between the gate stack and the substrate, the interfacial layer having a dopant same as the dopant in the outer and inner spacers.

20. The semiconductor device of claim 18, wherein a distribution of the k-value reduction impurities in the outer spacer and the inner spacer is a Gaussian distribution or complementary error function distribution.