GATE SPACER STRUCTURE AND METHOD OF FORMING SAME

• US 20200135889A1
• Filed: 01/11/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chien, Wei-Ting, Chen, Liang-Yin, Liu, Yi-Hsiu, Lee, Tsung-Lin, Chang, Huicheng
• Granted Patent: US 10,868,142 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02112 characterised by the material of the layer
• CPC Class Codes: H01L 21/02115 the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
• CPC Class Codes: H01L 21/02205 the layer being characterised by the precursor material for deposition
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/515 with cavities, e.g. containing a gas
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

Claims

1. A method comprising:

forming a sacrificial gate structure over an active region;

forming a first spacer layer along sidewalls and a top surface of the sacrificial gate structure;

forming a first protection layer over the first spacer layer;

forming a second spacer layer over the first protection layer;

forming a third spacer layer over the second spacer layer;

replacing the sacrificial gate structure with a replacement gate structure; and

removing the second spacer layer to form an air gap between the first protection layer and the third spacer layer.

2. The method of claim 1, further comprising forming a second protection layer between the second spacer layer and the third spacer layer.

3. The method of claim 2, wherein the first protection layer and the second protection layer comprise a same material.

4. The method of claim 2, wherein the first protection layer and the second protection layer comprise different materials.

5. The method of claim 1, wherein forming the first protection layer over the first spacer layer comprises depositing a carbon layer or a boron layer over the first spacer layer.

6. The method of claim 1, wherein removing the second spacer layer comprises performing a selective etch process on the second spacer layer.

7. The method of claim 1, further comprising, before forming the third spacer layer, forming an epitaxial source/drain region in the active region adjacent the sacrificial gate structure.

8. A method comprising:

forming a sacrificial gate structure over an active region;

depositing a first spacer layer along sidewalls and a top surface of the sacrificial gate structure;

doping an upper portion of the first spacer layer to form a first protection layer over an un-doped portion of the first spacer layer;

depositing a second spacer layer over the first protection layer;

forming an epitaxial source/drain region in the active region adjacent the sacrificial gate structure;

depositing a third spacer layer over the second spacer layer and the epitaxial source/drain region;

replacing the sacrificial gate structure with a replacement gate structure; and

performing a selective etch process on the second spacer layer to form an air gap between the first protection layer and the third spacer layer.

9. The method of claim 8, further comprising forming a second protection layer between the second spacer layer and the third spacer layer.

10. The method of claim 9, wherein forming the second protection layer comprises depositing a carbon layer or a boron layer.

11. The method of claim 8, wherein doping the upper portion of the first spacer layer comprises doping a material of the first spacer layer with carbon or boron.

12. The method of claim 8, wherein an etch rate of the first protection layer is less than an etch rate of the un-doped portion of the first spacer layer with respect to the selective etch process.

13. The method of claim 8, wherein doping the upper portion of the first spacer layer comprises performing a plasma-assisted doping process on the first spacer layer.

14. The method of claim 8, wherein forming epitaxial source/drain region comprises:

etching the first spacer layer, the second spacer layer, the first protection layer and the active region to form a recess; and

epitaxially growing a semiconductor material in the recess.

15. A device comprising:

a gate structure over an active region;

a first spacer extending along a sidewall of the gate structure and a top surface of the active region;

a first protection layer adjacent the first spacer, the first spacer being interposed between the sidewall of the gate structure and the first protection layer;

a second spacer adjacent the first protection layer, the first protection layer being interposed between the first spacer and the second spacer; and

an air gap interposed between the first protection layer and the second spacer.

16. The device of claim 15, further comprising a second protection layer between the first protection layer and the second spacer.

17. The device of claim 16, wherein the air gap is interposed between the first protection layer and the second protection layer.

18. The device of claim 16, wherein the second protection layer is a carbon layer or a boron layer.

19. The device of claim 15, wherein the first protection layer is a carbon layer or a boron layer.

20. The device of claim 15, wherein the first spacer is formed of a first material, and wherein the first protection layer is formed of the first material doped with carbon or boron.