METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES

• US 20200135891A1
• Filed: 10/15/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: PENG, Cheng-Yi, CHEN, Wen-Yuan, HSIEH, Wen-Hsing, HSU, Yi-Ju, HO, Jon-Hsu, LEE, Song-Bor, TIEN, Bor-Zen
• Granted Patent: US 11,069,791 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a plurality of fin structures over a semiconductor substrate, the plurality of fin structures extending along a first direction and arranged in a second direction crossing the first direction;

forming a plurality of sacrificial gate structures extending in the second direction over the fin structures;

forming an interlayer dielectric layer over the plurality of fin structures between adjacent sacrificial gate structures;

cutting the sacrificial gate structures into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction; and

forming gate separation plugs by filling the gate end spaces with two or more dielectric materials,

wherein the two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

2. The method according to claim 1, further comprising, after the gate separation plugs are formed:

removing the plurality of pieces of sacrificial gate structures to form gate spaces;

removing the first layer from the gate spaces; and

after the first layer is removed, forming metal gate structures in the gate spaces.

3. The method of claim 2, wherein the first layer is made of silicon oxide.

4. The method of claim 3, wherein the second layer is one of SiOC, SiOCN, SiCN or a porous material.

5. The method of claim 2, wherein the metal gate structures are in contact with the second layer.

6. The method of claim 1, wherein the two or more dielectric materials further includes a third layer having a different dielectric constant than the second layer.

7. The method of claim 6, wherein the first, second and third layers are, in this order:

silicon oxide, SiOCN and silicon oxide;

silicon oxide, porous material and silicon oxide;

silicon oxide, SiOCN and porous material;

or

silicon oxide, porous material and SiOCN.

8. The method of claim 1, wherein:

each of the plurality of sacrificial gate structures includes a sacrificial gate dielectric layer and a sacrificial gate electrode layer,

after the gate end spaces are formed, the sacrificial gate dielectric layer remains at bottom of the gate end spaces, and

the first layer is formed on the remaining sacrificial gate dielectric layer.

9. A method of manufacturing a semiconductor device, comprising:

forming a plurality of fin structures over a semiconductor substrate, the plurality of fin structures extending along a first direction and arranged in a second direction crossing the first direction;

forming a plurality of sacrificial gate structures extending in the second direction over the fin structures;

forming an interlayer dielectric layer over the plurality of fin structures between adjacent sacrificial gate structures;

removing the plurality of sacrificial gate structures to form gate spaces;

forming metal gate structures in the gate spaces;

cutting the metal gate structures into a plurality of pieces of metal gate structures by forming gate end spaces along the second direction; and

forming gate separation plugs by filling the gate end spaces with two or more dielectric materials,

wherein the two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

10. The method of claim 9, further comprising:

forming a fin liner layer over the plurality of fin structures; and

forming an isolation insulating layer such that upper portions of the fin structures are exposed,

wherein the gate end spaces penetrate the isolation insulating layer.

11. The method of claim 10, wherein the gate end spaces reach the fin liner layer.

12. The method of claim 10, wherein the gate end spaces penetrate the fin liner layer and reach the substrate.

13. The method of claim 9, wherein:

the first layer is made of silicon oxide, and

the second layer includes one or more layer of SiOC, SiOCN, SiCN or a porous material.

14. The method of claim 9, wherein a thickness of the first layer is smaller than a thickness of the second layer.

15. A semiconductor device, comprising:

a first fin field-effect transistor (Fin FET) including a first fin structure extending in a first direction and a first gate structure, the first gate structure including a first gate dielectric layer formed over the first fin structure and a first gate electrode layer formed over the first gate dielectric layer and extending in a second direction perpendicular to the first direction;

a second Fin FET including a second fin structure extending in the first direction and a second gate structure, the second gate structure including a second gate dielectric layer formed over the second fin structure and a second gate electrode layer formed over the second gate dielectric layer and extending in the second direction; and

sidewall spacers extending in the second direction, between which the first and second gate structures are disposed, wherein;

the first gate structure and the second gate structure are aligned along the second direction and are separated by a separation plug made of an insulating material,

the separation plug includes a first layer and a second layer formed on the first layer, and

a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

16. The semiconductor device of claim 15, wherein the first layer is made of silicon oxide.

17. The semiconductor device of claim 16, wherein the second layer is one of SiOC, SiOCN, SiCN or a porous material.

18. The semiconductor device of claim 16, wherein the first and second gate structures are in direct contact with the second layer.

19. The semiconductor device of claim 15, wherein the separation plug further includes a third layer having a different dielectric constant than the second layer on the second layer.

20. The semiconductor device of claim 19, wherein the first, second and third layers are, in this order:

silicon oxide, SiOCN and silicon oxide;

silicon oxide, porous material and silicon oxide;

silicon oxide, SiOCN and porous material;

or

silicon oxide, porous material and SiOCN.